Bibin Paul — CEO

Senior Principal-level High-Speed Serial Interface and SoC Design Engineer with 14.5+ years of experience delivering first-pass silicon across complex mixed-signal SoCs and high-speed interfaces. Strong expertise in architecture, PCS design, RTL implementation, and silicon execution for multi-protocol PHYs and custom retimer solutions. Specialized in TX/RX datapath architecture for multi-Gbps interfaces (~10–11 Gbps), including elastic buffers, aligners, gearboxes, PIPE interfaces, clock/reset architecture, and robust data-path design for Gen1/Gen2 operation. Hands-on experience with encoding/decoding schemes (128b/132b, 8b/10b), scramblers, and PRBS-based BIST for BER validation and debug. Deep experience in control-path design for multi-lane SerDes, covering TX/RX analog controllers, CDR control, calibration and bring-up sequencers, message-bus operations, and PHY–retimer interactions. Designed controllers and calibration algorithms for mixed-signal blocks such as high-speed clock recovery circuits and PLLs, with strong involvement in integration and silicon bring-up. Design of protocol-agnostic high-speed framing subsystems, including frame structure definition, TX/RX framing logic, bandwidth optimization, and clean system-level interfaces across PHY and retimer. End-to-end execution ownership spanning specification, micro-architecture, RTL design, block-level DV, top-level integration, lint/CDC closure, SDC development, STA reviews, GLS debug, ECO resolution, FPGA prototyping, and post-silicon validation. Known for strong debug methodology, observability-driven design, and predictable execution on first silicon. Recognized technical leader with experience in mentoring engineers, task planning, delegation, and automation, enabling high-quality and on-time delivery across cross-functional teams. Protocols & Interfaces: USB 3.1 (Gen1/Gen2), DisplayPort, PIPE 4.3/6.2, AMBA AXI/AHB/APB, I2C Domains: High-Speed Serial, SerDes, PHY, PCS, Retimers, Mixed-Signal SoCs

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in high-speed interfaces and SoC architecture.

Location: Bengaluru, Karnataka, India

Experience: 18 yrs 3 mos

Skills

High-speed Serial Interface Design
Soc Design
Post-silicon Debug
Digital Ic Design
Vlsi Design

Career Highlights

14.5+ years of experience in SoC design.
Expertise in high-speed serial interfaces and mixed-signal SoCs.
Proven track record of first-pass silicon success.

Work Experience

NXP Semiconductors

Senior Principal Engineer (3 yrs 5 mos)

Analog Devices

Staff Engineer/Technical Lead at Analog Devices (2 yrs 6 mos)

Digital IC Design Engineer (8 yrs)

Cadence Design Systems

Senior Digital Design Engineer (7 mos)

Wipro Technologies

VLSI Design Engineer (2 yrs 2 mos)

Govt.Rajiv Gandhi Institute of Technology Kottayam

Student (3 yrs 6 mos)

Education

Master of Technology - MTech at Indian Institute of Technology, Madras

Bachelor of Technology (BTech) at Government Rajiv Gandhi Institute of Technology Kottayam

AICBSE at St Peters Senior Secondary School, Kadayiruppu

Bibin Paul

CEO

Bengaluru, Karnataka, India18 yrs 3 mos experience

Highly Stable

Key Highlights

14.5+ years of experience in SoC design.
Expertise in high-speed serial interfaces and mixed-signal SoCs.
Proven track record of first-pass silicon success.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in high-speed interfaces and SoC architecture.

Contact

Skills

Core Skills

High-speed Serial Interface DesignSoc DesignPost-silicon DebugDigital Ic DesignVlsi Design

Other Skills

AHBAMBA AHB SoCAMBA AXIAPBASICATPGAXI-ECC BridgeAutomatic Test Pattern Generation (ATPG)BIST logicCDC analysisCadence VirtuosoChipscopeControl Path DesignDFT architectureData Path Design

About

Experience

18 yrs 3 mos

Total Experience

3 yrs 8 mos

Average Tenure

3 yrs 5 mos

Current Experience

Nxp semiconductors

Senior Principal Engineer

Nov 2022 – Present · 3 yrs 5 mos · Bengaluru, Karnataka, India

As part of the R&D team, specialized in architecture, design, and implementation of high-speed serial interfaces, with strong ownership of PCS architectures for multi-protocol PHYs and custom USB retimer solutions.
Led TX and RX datapath architecture and RTL design for ~10 Gbps interfaces, including elastic buffers, aligners, gearboxes, PIPE (4.3/6.2) interfaces, encoding/decoding schemes (128b/132b, 8b/10b), scramblers, and PRBS generator/checker–based BIST logic. Owned clock/reset architecture and datapath robustness across Gen1/Gen2 operation.
Designed and implemented control paths for multi-lane SerDes supporting USB and DisplayPort, including TX/RX analog controllers, CDR control logic, calibration sequencers, message-bus operations, and USB retimer–PHY interactions. Developed controllers and calibration algorithms for mixed-signal blocks such as high-speed clock recovery circuits (~11 Gbps) and PLLs, supporting integration and bring-up.
Architected and delivered a protocol-agnostic high-speed framing subsystem, including TX/RX framing logic, frame structure definitions, bandwidth optimization, and clean interfacing with the USB retimer and PHY subsystems.
Drove subsystem specifications and micro-architecture, RTL implementation, block-level DV, top-level integration, lint/CDC closure, SDC development, STA reviews, GLS debug, and ECO resolution in close collaboration with PD, DV, and validation teams. Designed debug and observability logic to accelerate silicon validation and FPGA prototyping, enabling efficient root-cause analysis during bring-up.
Actively improved execution efficiency through automation and provided technical leadership and mentorship, including task definition, delegation, design reviews, and progress tracking for junior engineers. Delivered consistent first-pass silicon success across all assigned designs.
Protocols & Interfaces: USB 3.1 (Gen1/Gen2), DisplayPort, PIPE 4.3/6.2, AHB, APB, I2C

USB 3.1 (Gen1/Gen2)DisplayPortPIPE 4.3/6.2AHBAPBI2C+5

Analog devices

2 roles

Staff Engineer/Technical Lead at Analog Devices

Promoted

May 2020 – Nov 2022 · 2 yrs 6 mos

Staff Design Engineer with deep experience in SoC RTL design, silicon execution, and post-silicon debug across Ethernet SoCs, Cortex-M–based radio platforms, audio, touch, and custom silicon products.
Owned clock/reset architecture, CDC strategy, custom IP design, and debug logic across multiple SoCs. Played a key role in post-silicon root-cause analysis, ECO definition, and verification of fixes using STA-driven analysis and SPICE simulations. Contributed to SoC-level DFT architecture (Scan & MBIST), including RTL ownership, ATPG, SDC constraints, and GLS simulations, leading to improved coverage and first-pass silicon success. Invented the Single Pin Scan Controller, significantly reducing test pin requirements. Led and mentored a 3-member DFT team and represented technical solutions in customer-facing and internal reviews.

SoC RTL designsilicon executionpost-silicon debugECO definitionSTA-driven analysisSPICE simulations+2

Digital IC Design Engineer

Apr 2014 – Apr 2022 · 8 yrs

Cadence design systems

Senior Digital Design Engineer

Sep 2013 – Apr 2014 · 7 mos · Banglore, India

Senior Design Engineer working on MIPI D-PHY SoC IP, contributing across synthesis, timing constraints, and verification support.
Handled SpyGlass lint/CDC, block-level SDC development, synthesis, and unit-level testbench development. Supported functional modeling of analog blocks, dot-lib creation, and netlist extraction/correlations.

MIPI D-PHY SoC IPsynthesistiming constraintsverification supportDigital IC Design

Wipro technologies

VLSI Design Engineer

Jul 2011 – Sep 2013 · 2 yrs 2 mos · KOCHI

RTL Design Engineer contributing to multiple high-performance IPs including equilization controller for PCIe Gen3, AXI-ECC Bridge, multiple blocks for MIPI M-PHY, and AMBA AHB SoC for Renesas Electronics Japan
Owned micro-architecture and RTL design of protocol controllers, encoders/decoders, FIFOs, and interface logic. Actively involved in requirement analysis with customers, top-level integration, CDC assertions, lint checks, synthesis, and DFT readiness. Delivered high-quality RTL with strong customer satisfaction, earning recognition for execution excellence and technical contributions.

RTL DesignPCIe Gen3AXI-ECC BridgeMIPI M-PHYAMBA AHB SoCVLSI Design