Apr 2016 – Present · 10 yrs · Bangalore

• Presently working as Technical Leader and Architect for Pre-Si Verification of GPU based AI Accelerator product (named as Jaguar Shores). This product is 3nm technology based and is using Ultra Accelerator Link (UAL) for creating Scale-Up systems and PCIE-Gen7 to create Scale-Out systems along with HBM4 while designing the Rack Scale GPU based Data center for Computing.
• Worked as Technical Leader and Architect for Pre-Silicon Verification of 5nm technology based SERVER SoC Diamond Rapid (DMR).
• Worked as Technical Leader for Pre-Silicon Verification of 7nm technology based SERVER SoC Granite Rapid and Sapphire Rapid (GNR and SRF).
• Worked as Technical Leader for Pre-Silicon Verification of 10nm technology based SERVER SoC ICELAKE SP (ICSXP).
• Areas of Expertise:
• Understand the complete Architecture and Functional details of SOC and then define the Test plan for exhaustive End-to-End Verification of SOC.
• Define complete micro level architecture of the SOC Level Testbench and Stimulus using System Verilog and UVM (including Git based repository and version control system, XPROP, UPF based Power Aware Simulation, SV assertions, Functional and Code coverage) and technically lead the complete development effort.
• Develop the Multi-Die (Multi-Chip) Package level Verification environment using Synopsys VCS Distributed Simulation flow.
• Architectural and functional understanding of GPU based AI accelerators and CPU based Servers product being used in General Purpose Computing.
• Expertise in SOC level Verification of the Power Management and Low Power flows, Ultra Chip Interconnect Express (UCIe) block, Reset/clock/Fuse blocks, PCIE Gen6/7 and Ultra Accelerator Link (UAL1.0) blocks.
• Understanding of ARM tool chain/boot strap code, ARM interrupt functions/handlers, debugging/achieving Booting by Cortex-A9/A53/A57 Processers from various boot devices (like Serial flash, Parallel NAND Flash, EMMC etc.) in SOC level simulation environment.