Venkatesh R

Software Engineer

Bengaluru, Karnataka, India9 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Physical Design and Static Timing Analysis.
  • Proficient with industry-standard tools like Synopsys and Calibre.
  • Strong background in VLSI and Digital Design methodologies.
Stackforce AI infers this person is a VLSI design engineer with expertise in physical design and timing analysis.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

RedhawkSynopsys toolsDesign Rule Checking (DRC)Layout Versus Schematic (LVS)InnvousCalibreLECLogic SynthesisCMOSDigital DesignsVHDLVery-Large-Scale Integration (VLSI)CCTS

Experience

9 yrs 10 mos
Total Experience
4 yrs 11 mos
Average Tenure
8 yrs 1 mo
Current Experience

Qualcomm

3 roles

Staff Engineer

Promoted

Nov 2024 – Present · 1 yr 5 mos

RedhawkSynopsys toolsDesign Rule Checking (DRC)Layout Versus Schematic (LVS)InnvousCalibre+10

Lead Sr Engineer

Nov 2021 – Nov 2024 · 3 yrs

RedhawkSynopsys toolsDesign Rule Checking (DRC)Layout Versus Schematic (LVS)InnvousCalibre+10

Senior Engineer

Mar 2018 – Nov 2021 · 3 yrs 8 mos

  • physical design/STA/signoff
Design Rule Checking (DRC)Layout Versus Schematic (LVS)Physical DesignStatic Timing Analysis

Intel corporation

Physical Design Engineer

Jun 2016 – Mar 2018 · 1 yr 9 mos

  • Block level Implementation
Synopsys toolsInnvousPhysical Design

Education

JNTUH College of Engineering Hyderabad

MASTERS — VLSI System Design

Jan 2012 – Jan 2014

Jawaharlal Nehru Institute of Technology

Bachelor's — Electronics and Communication Engineering

Jan 2007 – Jan 2011

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