F Shree

Product Engineer

Chennai, Tamil Nadu, India4 yrs 3 mos experience

Highly Stable

Key Highlights

Experienced in VLSI design and verification.
Technical blog writer with mentoring experience.
Guest lecturer providing interview tips.

Stackforce AI infers this person is a VLSI Design and Verification Engineer with a focus on technical training.

Contact

Skills

Core Skills

Design Verification

Other Skills

SystemVerilogAPB protocolsAxpEDAAXIAMBASVVery-Large-Scale Integration (VLSI)VerilogUvm

Experience

4 yrs 3 mos

Total Experience

4 yrs

Average Tenure

3 mos

Current Experience

Globallogic

Senior Verification Engineer

Jan 2026 – Present · 3 mos · Chennai, Tamil Nadu, India · On-site

Tessolve

Design Verification Engineer

Jan 2022 – Jan 2026 · 4 yrs · Chennai, Tamil Nadu, India · Hybrid

SystemVerilogAPB protocolsDesign Verification

Education

Sathyabama Institute of Science & Technology, Chennai

Master of Engineering - MEng — Embedded system and IoT

Nov 2020 – Apr 2022

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