Poojitha Munaga — Software Engineer
Worked on TSMC 6nm and 7nm technologies. • Responsible for all aspects of Physical Design for Blocks covering Floor planning, Placement, Clock tree synthesis/clock gating, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks, EM/IR, DRC, LVS, ERC analysis & fixes • Complete signoff (Timing, PV and IR) • Physical Verification (DRC, LVS, Antenna, ERC)
Stackforce AI infers this person is a Physical Design Engineer specializing in semiconductor technologies.
Location: Bangalore Urban, Karnataka, India
Experience: 8 yrs 1 mo
Skills
- Physical Design
- Timing Analysis
Career Highlights
- Expertise in TSMC 6nm and 7nm technologies.
- Proficient in Physical Design and verification processes.
- Strong background in low power design techniques.
Work Experience
MediaTek
Staff Engineer (1 yr 10 mos)
Sr.Engineer (4 yrs 4 mos)
SOCTRONICS TECHNOLOGIES PRIVATE LIMITED
Engineer 2 (3 yrs 4 mos)
VEDA IIT
Trainee in veda IIT (5 mos)
Education
Bachelor of Technology at Lakireddy Bali Reddy College of Engineering(Autonomous)
Bachelor of Technology - BTech at Lakkireddy Balireddy college of engineering
