Kumar Sunny

Software Engineer

Bengaluru, Karnataka, India3 yrs 7 mos experience
Most Likely To Switch

Key Highlights

  • Expert in RTL design and verification.
  • Strong background in microelectronics and VLSI design.
  • Proficient in multiple programming languages and tools.
Stackforce AI infers this person is a VLSI design engineer with expertise in RTL design and verification.

Contact

LinkedIn

Skills

Other Skills

LINTLinuxUnixSilvacoCadence VirtuosoRISC-VIncident ManagementStatic Timing AnalysisVerilogC (Programming Language)IBM MainframeIBM SPUFISQLServiceNowIBM Db2

Experience

3 yrs 7 mos
Total Experience
1 yr 9 mos
Average Tenure
1 yr 10 mos
Current Experience

Mediatek

2 roles

RTL Design Engineer

Jul 2024 – Present · 1 yr 10 mos · Bengaluru, Karnataka, India · On-site

RTL Design Engineer

Jul 2023 – Jul 2024 · 1 yr · Bengaluru, Karnataka, India · On-site

Tata consultancy services

Production Support Engineer

Feb 2021 – Nov 2022 · 1 yr 9 mos · Kolkata

Education

Motilal Nehru National Institute Of Technology

Master of Technology - MTech — MICROELECTRONICS & VLSI DESIGN

Aug 2022 – May 2024

Techno Main - Salt Lake

Bachelor of Technology - BTech — ELECTRONICS & COMMUNICATION ENGINEERING

Aug 2016 – Jul 2020

Stackforce found 100+ more professionals with LINT & Linux

Explore similar profiles based on matching skills and experience

VIVEK PANDIT

VIVEK PANDIT

Software Engineer II

at Cadence Design Systems

Noida, India9 yrs 9 mos exp
RTL DesignTest PlanningVerificationVerification Tool Development
Abhishek Raj Sahoo

Abhishek Raj Sahoo

CPU Design Engineer

at Apple

Cupertino, United States8 yrs 9 mos exp
Static Timing AnalysisSynthesisTiming Closure
Deeksha Tiwari

Deeksha Tiwari

SoC Design Intern

at Intel Corporation

Gurgaon, India0 mo exp
VLSI Physical Design
Vasundhra Kaushal

Vasundhra Kaushal

Lead Design Engineer

at NXP Semiconductors

Noida, India10 yrs 6 mos exp
Physical DesignRTL Design
Dharmendra Kumar

Dharmendra Kumar

SOC Design Engineer

at Intel Corporation

Bengaluru, India12 yrs 11 mos exp
RTL DesignMicroarchitectureLogic SynthesisStatic Timing Analysis
Satyam Prasad

Satyam Prasad

FPGA Silicon Design Engineer

at Altera

Bengaluru, India5 yrs 7 mos exp
RTL DesignDFT
SHAMBHUROHITH KUMAR B N

SHAMBHUROHITH KUMAR B N

Senior Application Specific Integrated Circuit Engineer

at NVIDIA

Bengaluru, India3 yrs 9 mos exp
RTL CodingRTL Verification
Pg Vinay Kumar

Pg Vinay Kumar

Senior Engineer

at MediaTek

Adoni, India7 yrs 11 mos exp
RTL DesignLogic Synthesis