VIVEK PANDIT

Software Engineer

Noida, Uttar Pradesh, India9 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 8 years of experience in RTL Design Verification.
Expert in UVM based verification environment development.
Proficient in automating verification processes with Perl and C++.

Stackforce AI infers this person is a Verification Engineer specializing in RTL Design and EDA tool development.

Contact

panditvivek02@yahoo.com LinkedIn

Skills

Core Skills

VerificationTest PlanningRtl DesignVerification Tool Development

Other Skills

AMBA AHBAMBA APBAMBA AXIAMBA AXI5AMBA Bus ProtocolARMv-8 ArchitectureASICAssembly LanguageAudio Video SystemsCC++Cache-line Migration AnalysisCoverage AnalysisDiptraceEmbedded Systems

About

👉 Design Verification (DV) Engineer with total 8+ years of solid work experience in verifying IP (Block) / Subsystem / SoC Level RTL Design, Also Experience in EDA tool development & tool Validation. 👉 My Experience with Details are as below : ✔ Hands on Experience with UVM Based Verification Environment Development from Scratch. ✔ Experience in Bringing up UVM Based Verification Environment for a New Project, UVM Based Sequence/Test Writing, Scoreboard development (with C Reference Model), Monitor and TB Top development. Running Test Regressions & Debugging Failures. ✔ Experience in Writing Feature Plan, Test Plan, Coverage plan and Assertion Plan from a Spec. ✔ Experience in Writing System Verilog Assertions (SVA) & Functional Coverage. ✔ Hands on Experience with Functional Coverage and Toggle Coverage analysis and closure for holes. ✔ Synopsys AXI VIP Integration with IP Verification Environment. ✔ Hands on Experience with Cadence LINT (Superlint) Rule/Check/Tag validation with Verilog/SV/VHDL. ✔ Experience in Subsystem level RTL integration to SoC. ✔ Developed Bandwidth Tracker for one of DDR Subsystem Project. ✔ Handling weekly regression system & Interacting to team with Report. ✔ Hands on Experience with Automation infrastructure development with Perl and C++ ✔ Experience with Top Level Verification of ARMv8 based CPU (Core) ✔ Experience in Development of RIS Tool for UNIX Environment using Perl and C++ ✔ Experience in Mentoring new team members & bringing up on a Project. 👉👉 Looking for a new opportunity in RTL Design Verification (DV) domain on immediate basis.

Experience

9 yrs 9 mos

Total Experience

4 yrs 10 mos

Average Tenure

7 yrs 4 mos

Current Experience

Cadence design systems

Software Engineer II

Jan 2019 – Present · 7 yrs 4 mos · Noida Area, India

Validation of Type Coverage feature implemented for vManager/IMC.
Creating Test Plan for Type Coverage feature for both Formal and Simulation coverage.
Writing test cases in SV/Verilog, to verify the feature.
LINT (Superlint) Rule/Check/Tag validation.
Created Test Plan for 45+ checks & Writing test cases in SV/Verilog/VHDL for same.
Running created tests with SuperLINT tool. Reporting bug to designer with fix.
Cadence’s VIP & Assertion Based VIP (ABVIP) Correlation validation for new feature of AXI5.
Creating Test Plan for new features of AMBA AXI5 & Writing UVM based test cases.

Type CoverageTest Plan CreationSV/VerilogLINT ValidationAMBA AXI5UVM+2

Arm

2 roles

Graduate Engineer

Jul 2016 – Jan 2018 · 1 yr 6 mos · Bengaluru Area, India

Worked on Top Level Verification of ARMv8 based Core/CPU. Highlights for this role are :
Test scenario development, modifying/adding an existing template, generating random test cases with it, running it on core/RTL, analyzing and debugging failures.
Working closely with RTL designer/team for filed RTL bug until it resolves.
Top level template development for RIS tool to recreate corner case RTL bug.
Writing System Verilog based coverage for system registers.
Wrote System Verilog based assertion.
Writing directed test cases to hit particular scenario.
Function coverage collection, analysis and closer for holes.
Toggle coverage collection for Top Level IO pins of core and closer for any hole.
Creating/Adding new patch to change test case behavior run time.
Automated coverage files merging and test case filtering based on requirement with Perl and C++.
Implemented designs in SV and using UVM to create verification environment for same.
Mentored new team members on ARM based core overview, validation flow, using debugging tool effectively, categorizing and debugging failures.

Top Level VerificationTest Scenario DevelopmentSystem VerilogUVMCoverage AnalysisPerl+3

Intern

Jun 2015 – May 2016 · 11 mos · Bengaluru Area, India

Worked on Development of Multiprocessor verification RIS Tool. Specifically worked on development of utilities for it which are capable to :
 Generation of Corner-Case test sets for all precision FP verification.
This utility 'll generate test-sets that can generate test stimuli targeting corner case scenarios in
the FP verification.
This approach uses a random constrained approach, where the exponent is subject to certain
bound taking into consideration the precision which determines the floating point format.
 Analysis of cache-line migration events in Multi-Core Verification.
This utility parses the simulation traces and graphically depicts the collision events to regions that
were accessed within a test from the different processing elements.
It also acts as an additional QA check, to ensure that intent of verification was met.
 Enhanced functionality in the QA process for the RIS tool.
Developed some basic Important checks for the Test Generated by MP RIS Tool.
 Optimized the QA utility and gained a performance improvement of over 4x in terms of execution
speed.