Abhishek Raj Sahoo

CEO

Cupertino, California, United States8 yrs 7 mos experience

Most Likely To Switch

Key Highlights

Over four years of experience in VLSI industry.
Expertise in Static Timing Analysis and Timing Closure.
Proven track record in leading teams and mentoring interns.

Stackforce AI infers this person is a VLSI engineer with expertise in timing analysis and closure for complex SoCs.

Contact

Skills

Core Skills

Timing ClosureStatic Timing AnalysisSynthesis

Other Skills

Algorithm DevelopmentApplication-Specific Integrated Circuits (ASIC)CC++CDCComputer ArchitectureConstraints CodingConstraints GenerationConstraints ValidationECO CreationLintLint AnalysisMachine LearningMatlabMicroelectronics

About

Hardware engineer by profession, having a demonstrated history of working in the VLSI industry with four plus industry experience in Static Timing Analysis, building timing constraints, and the validation via Primetime and Design Compiler. After my undergraduate studies, I joined Intel India in the HSPE group, working for three years and responsible for the timing closure of complex SoCs like the CPU, Server, and Modem chips. Worked in Texas Instruments in the Radar business unit for one and half years, responsible for Synthesis, Timing closure, Constraints Coding, and Validation via Cadence tools like Genus and Tempus. After four years of working in the industry, I joined the University of California San Diego to pursue a Master's in Electrical and Computer Engineering. I am pursuing courses specializing in Timing Closure, Power analysis, optimization techniques, Synthesis of Complex SoCs, and Computer Architecture. I can be reached out at below contact details. Email: arsahoo (at) ucsd (dot) edu

Experience

Apple

2 roles

CPU Design Engineer

Feb 2024 – Present · 2 yrs 1 mo · Cupertino, California, United States · On-site

CPU STA

Jun 2023 – Sep 2023 · 3 mos · San Francisco Bay Area · On-site

Timing ClosureMachine LearningStatic Timing Analysis

Uc san diego jacobs school of engineering

Graduate Student

Sep 2022 – Dec 2023 · 1 yr 3 mos · San Diego, California, United States

Texas instruments

Digital Design Engineer

Mar 2021 – Aug 2022 · 1 yr 5 mos · Bengaluru, Karnataka, India

Led a team of 4 for final timing closure, and mentored an intern to work on
Constraints Demotion flow and timing Correlation Engine
Developed an intelligent IO budgeting algorithm to generate subchip IO
constraints based on logic depth and distance for precise block level closure
Responsible for Constraints Coding, Validation and Synthesis of complex
sub-chips, and working closely with RTL/DFT team for architectural feedbacks.
Timing analysis, ECO generation and ensure a smooth sign-off of the SoC

Intel corporation

2 roles

STA Engineer

Promoted

Jun 2019 – Mar 2021 · 1 yr 9 mos

PT-ECO and manual-ECO creation for setup/hold fix, verify ECO across all
modes/corners to avoid potential impact at SoC level.
Partition timing analysis feedback for both internal/interface paths in synchronization with PD/RTL/DFx based on feedbacks.
Constraints generation and validation, coding exceptions and verifying them in
EDA tools like Primetime and Design Compiler
Partition vs Full Chip Timing mis-correlation debug in case FEP/WNS is not
matching b/w block PT run flat SOC PT run
Maintained checks and balance in the system for SOC timing convergence
signoff

Component Design Engineer

May 2018 – May 2019 · 1 yr

Part of the Modem Design team. Currently working in 7nm and 14 nm technology node. Responsible for input/output constraints coding and validation for 4G/5G subsystems. Developed shell scripts to automate the Input/Output constraints tcl files, modifying IO delays for relevant ports (Combo ports, feedthrough ports) to meet the timing requirements, and validation of the constraints for all the four modes using DC(Design Compiler) and PT(Prime Time) Synopsys tools. Performed Lint and Clock Domain Crossing (CDC) analysis using Spyglass tool by Synopsys as a static checks of the design verilog files.