Bhavana Surya — Software Engineer
ASIC Design Verification Engineer with over 3 years of experience at the IP level. Skilled in SystemVerilog, UVM and VCS for developing and debugging testbenches. Worked with AMBA protocols. Emphasis on thorough verification and well-structured testbench development.
Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in ASIC and digital electronics.
Location: Bangalore Urban, Karnataka, India
Experience: 4 yrs 1 mo
Skills
- Asic Verification
- Systemverilog
Career Highlights
- Over 3 years of ASIC design verification experience.
- Expert in SystemVerilog and UVM for testbench development.
- Strong focus on thorough verification processes.
Work Experience
MediaTek
Verification Engineer (4 yrs 1 mo)
Education
VLSI Design and Verification Trainee at Maven Silicon
Bachelor of Engineering - BE at East West Institute of Technology, BANGALORE
