Ruchi Tilwankar

Product Engineer

India8 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC design and physical implementation.
Proficient in timing analysis and signal integrity.
Hands-on experience with leading Synopsys tools.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and physical design.

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Skills

Core Skills

Asic FlowStatic Timing AnalysisPhysical DesignDigital Circuit Design

Other Skills

floorplaningPowerplanningDSM technolgyTiming driven placementCongestion removalCrosstalk analysisMCMM and OCV analysisSynopsys PrimetimeSynopsys toolsSynopsys IC CompilerFalse pathMulti-cycle multi-frequency pathsFixing setup and hold violationsSignal IntegrityClock Tree Synthesis

Experience

8 yrs 3 mos

Total Experience

4 yrs 1 mo

Average Tenure

7 yrs 9 mos

Current Experience

Intel corporation

Library Design Engineer

Jul 2018 – Present · 7 yrs 9 mos · Bangalore

Asic flowStatic Timing AnalysisfloorplaningPowerplanningDSM technolgyTiming driven placement+25

Rv-vlsi vlsi and embedded systems design center

Physical Design Engineer Trainee

Jul 2017 – Jan 2018 · 6 mos · Bengaluru Area, India

Physical implementation of a block level design. 40nm Technology, 34 macros, 46204 standard cells, clock frequency 833MHz, supply voltage 1.1V, 6 metal layers, max IR-drop (Vdd + Vss) 5%, power budget 600mW.

Crisp

Trainee

Jul 2016 – Jul 2016 · 0 mo · Bhopal Area, India

Understanding Digital circuits and learning VHDL and Verilog in different modelling styles on FPGA. Designing layouts of basic logic gates in 45 micron technology.