Karthik C — Software Engineer

Trained Physical design engineer with exposure to the following fields: > Good Understanding of Physical design concepts ( floor planning, placement, CTS, routing) hands on experience in Synopsys ICC tools. > Good understanding of Static timing analysis (STA) and ability to interpret timing reports for setup and hold analysis. > Basic knowledge of Physical Verification (PV) with DRC and LVS checks. > Hands on Exposure to EDA tools ( IC Compiler, Primetime) > Good knowledge of CMOS and ASIC Design. • Project : Physical Implementation at Block level. Technology/Layers : 40nm/7 layers. Macros : 34 STD cells : 38887 No. of clocks : 5 Frequency : 833MHz Tools used : IC Compiler, Primetime. Role and Description : Block level Physical Design Engineer. > The Tasks handled were floor planning, place and route of the design, perform STA and bring the block to timing closure, clean DRC/LVS issues at Block level. > The Block has its own complexities with respect to Utilization and timing closure, Understanding STA concepts such as start points and end points for a particular path,timing arcs,Computing Cell Delays,Input slew and output load.Understanding concepts related to clock latency ,clock skew of flip-flops.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in ASIC development.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 7 mos