Jay Kapasi

Software Engineer

Hyderabad, Telangana, India16 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL Design and SOC Prototyping.
Proven track record in FPGA validation and driver development.
Strong background in embedded systems and high-speed interfaces.

Stackforce AI infers this person is a Semiconductor and Embedded Systems expert with a focus on RTL Design and SOC Prototyping.

Contact

Skills

Core Skills

Rtl DesignFpgaSoc PrototypingValidationDriver DevelopmentFpga DesignEmbedded Systems

Other Skills

VerilogEmbedded CC++CVHDLJavaJavaScriptMicrocontrollersC#SPICEPHPMySQLCSSJSPSQL

About

Interests: RTL Design, Pre & Post Silicon Validation, SOC Prototyping, Firmware & Software Architecture / Design, RTL Design - DSP algorithms viz. Filters, FFT, RADAR, High Speed interfaces viz. PCIe , SRIO, Interlaken, USB2, Gigabit transceivers, Low Speed interfaces viz. SPI, UART, FPGAs - Xilinx, Microsemi, Altera Firmware/Software - Peripheral drivers - USB, SPI, I2C,. RealTime DataViewer, Linux Porting SOC Prototyping - Automotive Switch, Microsemi FPGA/SoC, RISCV

Experience

16 yrs 9 mos

Total Experience

2 yrs 4 mos

Average Tenure

4 yrs 2 mos

Current Experience

Amd

MTS Silicon Design Engineer

Feb 2022 – Present · 4 yrs 2 mos · Hyderabad, Telangana, India

VerilogRTL DesignFPGA

Xilinx

Senior Design Engineer

Nov 2018 – Feb 2022 · 3 yrs 3 mos · Hyderabad Area, India

VerilogRTL DesignFPGA

Microsemi corporation

Senior Validation Engineer

Feb 2017 – Nov 2018 · 1 yr 9 mos · Hyderabad Area, India

High speed FPGA SERDES Validation along with Interlaken protocol validation with InterOp.
SOC Prototyping of a RISC V based multicore(1+4) processor subsystem with a set of High speed peripherals like USB/SDEMMC/GEM and low speed peripherals like UART/I2C/CAN/SPI/QSPI

VerilogSOC PrototypingValidation

Mistral solutions pvt. ltd

Module Lead

Mar 2015 – Jan 2017 · 1 yr 10 mos · Bengaluru, Karnataka, India

Requirement analysis, Guiding design engineers, FPGA RTL Design
Windows driver development for PCIe using WDK to support Autonomous DMA function.
Development of PCIe-DMA driver for VxWorks OS and integration with User Application.
SOC prototyping of a managed multiport switch.

VerilogRTL DesignDriver Development

Bit mapper integration technologies pvt. ltd

Design Engineer

Oct 2011 – Mar 2015 · 3 yrs 5 mos · Pune Area, India

Worked on FPGA RTL Design, Embedded C Coding and GUI design.
Real time data acquisition system with all the components from FPGA, Embedded processor code and GUI designed and architected from scratch.
Implementation of cross correlation algorithm using FFT in Virtex 7 FPGA along with peak detection algorithm. Data was processed at 720 MSPS and algorithm was able to acheive performance beyond specified execution time by a huge margin.

VerilogFPGA DesignEmbedded Systems

Dhirubhai ambani institute of information and communication technology

Teaching Assistant

Jul 2009 – Jul 2011 · 2 yrs · Ahmedabad Area, India

I have to handle lab and explain the aim of the lab to students as well as help them during their lab exercise and solve any problems they have encountered. It was a great learning experience for me. I was able to learn the teaching tactics and how to make student understand the real purpose for taking this lab.

Tata consultancy services

Software Engineer Intern

Dec 2008 – Apr 2009 · 4 mos · Gandhinagar

Here I was assigned some modules from a huge project which was build on J2EE framework with spring & hibernate. My responsibility was to write code for these modules as specified by our Project Lead.