Ashok Agineti

Software Engineer

Bengaluru, Karnataka, India9 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design and Static Timing Analysis.
Strong background in VLSI design and FPGA development.
Proven leadership and public speaking skills.

Stackforce AI infers this person is a VLSI and FPGA design engineer with expertise in physical design and timing analysis.

Contact

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

TCLPNRSignal IntegrityPrimetimeTiming ClosureHDL DesignerVHDLFPGAASICTcl-TkPerlCadence VirtuosoCadence Virtuoso Layout EditorField-Programmable Gate Arrays (FPGA)Verilog

Experience

9 yrs 4 mos

Total Experience

5 yrs 7 mos

Average Tenure

9 yrs 4 mos

Current Experience

Amd

Member of Technical Staff

Jul 2024 – Present · 1 yr 9 mos · Bangalore Urban, Karnataka, India

TCLPNRSignal IntegrityPrimetimeTiming ClosureStatic Timing Analysis+15

Intel corporation

Hardware Design Engineer

Dec 2016 – Present · 9 yrs 4 mos

Physical Design & STA Engineer

Timing ClosurePNRPhysical DesignStatic Timing Analysis

Education

Vellore Institute of Technology

Master of Technology (M.Tech.) — VLSI DESIGN

Jan 2014 – Jan 2016

Jawaharlal Nehru Technological University

Bachelor's Degree

Jan 2010 – Jan 2014

Narayana jr College

Associate's Degree — MPC

Jan 2008 – Jan 2010

Sarojini English Medium High School

High School — Tenth

Jan 2008 – Jan 2008

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