Amrut Jigajinni

Software Engineer

Bengaluru, Karnataka, India13 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Masters in VLSI Design with 3 years of experience.
Expertise in RTL implementation and verification.
Proficient in EDA tools and Static Timing Analysis.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC and digital design.

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Skills

Other Skills

VerilogVLSIDigital DesignsRTL designSynopsys toolsPerlStatic Timing AnalysisUnixCData StructuresLinuxXilinxFunctional VerificationRTL codingASIC

About

Masters in VLSI Design and around 3 years of experience in ASIC front end IP Design and Verification -- Good Knowledge of Front End ASIC Design and Verification -- Hands on experience in Implementing RTL and Verifying RTL modules using Bus Function Models(BFM's) in verilog -- Expertise in analyzing the Spyglass CDC checks -- Experience in writing Synthesis Design Constraints(SDC) -- Experience in working on EDA tools such as VCS, Design Compiler, Spyglass CDC -- Good Knowledge of Static Timing Analysis(STA) --- Familiar with Shell scripting, PERL and basic TCL Specialties: Digital Design, RTL implementation using Verilog HDL, Spyglass CDC, Synthesis, Verilog Test Bench.

Experience

13 yrs 6 mos

Total Experience

6 yrs

Average Tenure

9 yrs 10 mos

Current Experience

Intel corporation

Senior Design Engineer

Sep 2018 – Present · 7 yrs 8 mos · Bengaluru, Karnataka, India

Samsung semiconductor

Technical Lead

Apr 2017 – Present · 9 yrs 1 mo · Bengaluru, Karnataka, India

Samsung

Lead Design Engineer

Jul 2016 – Present · 9 yrs 10 mos · Bengaluru, Karnataka, India

RTL Designing for memory controllers

Synopsys

2 roles

ASIC Digital Design Engineer

Jun 2014 – Jul 2016 · 2 yrs 1 mo · Bangalore

Roles and Responsibilities as a part of USB 2.0 IP team:
Understanding the micro-architecture of IP Design
RTL Design in feature enhancements,support for RTL bug fixes and RTL coverage analysis
Ownership of fixing the Spyglass CDC violations
Ownership of Synthesis & fixing the Synopsys Design Constraints(SDC) for resolving timing violations
Roles and Responsibilities as a part of JPEG IP team :
Complete ownership of designing and implementing the RTL of Error Detection Algorithm for a decoded JPEG image
Customer Support for functional issues

Intern Technical

Jun 2013 – Jun 2014 · 1 yr · Bangalore

Project Involved : RTL implementation and Module level verification of DMA Controller for 10- Gigabit Ethernet MAC(XGMAC)
Description: The DMA designed here is a multichannel DMA which helps to achieve the required throughput of 10- Gigabit Ethernet MAC (XGMAC) and improve the system performance. The DMA Controller is divided into independent transmit engine and receive engine. DMA handles the Ethernet data packet transfer between the XGMAC core and the host system using the descriptors provided by the host application. DMA uses AXI interfaces to communicate with host and XGMAC core.
Responsibilities:
> Analyze the design document, understand the functionality of each individual module and implement the RTL using Verilog HDL
> Planning different test case and verifying each individual RTL module using Task based Bus Function Models(BFM) in Verilog
> Linting of the integrated RTL design module by module using LEDA tool
> Debugging of RTL modules to meet required functionality in the integrated environment
> Integration of RTL modules and Packaging according to different configurations and features
> Synthesis and Gate Level Simulations