sanjay kumar A

Software Engineer

Bengaluru, Karnataka, India6 yrs 5 mos experience

Key Highlights

  • Expert in ASIC design flow and physical design.
  • Significant improvements in DRC/LVS/TIMING resolution.
  • Proficient in Synopsys tools for semiconductor design.
Stackforce AI infers this person is a Semiconductor Design Engineer with strong ASIC design expertise.

Contact

Skills

Core Skills

Physical DesignAsic Design

Other Skills

SynthesisLogic SynthesisFloorplanPlacement & RoutingCTSTiming AnalysisSignal IntegrityECOSynopsys Fusion CompilerICC2PrimeTimeDesign Rule Checking (DRC)C (Programming Language)LECFusion Compiler

About

Our team at L&T Technology Services harnesses my robust expertise in ASIC design flow, mastering tools such as Synopsys Fusion Compiler and ICC2 to optimize complex physical layouts. With a foundation in Electrical, Electronics, and Communications Engineering from New Horizon College of Engineering, my approach integrates advanced technical skills with a focus on signal integrity and timing closure. Leveraging certifications in physical design, my contributions have led to significant improvements in DRC/LVS/TIMING resolution. We have enabled efficient multi-floorplan placement of macros, enhancing system performance. My dedication to continual learning and precision drives our pursuit of excellence in semiconductor design.

Experience

6 yrs 5 mos
Total Experience
2 yrs
Average Tenure
1 yr 6 mos
Current Experience

Mediatek

Senior Physical Design Engineer

Nov 2024Present · 1 yr 6 mos · On-site

L&t technology services

Senior Physical Design Engineer

Aug 2023Dec 2025 · 2 yrs 4 mos · Bengaluru, Karnataka, India · On-site

SynthesisLogic SynthesisPhysical DesignASIC Design

Hcl technologies

Physical Design Engineer

Apr 2021Jul 2023 · 2 yrs 3 mos · India

  • strong experience in asic design flow including synthesis, Floorplan, placement & routing, CTS,timing analysis, signal integrity & ECO
  • strong expertise in Synopsys tools like Fusion Compiler, ICC2, PrimeTime
  • Responsible for multi-floorplan placement of macros at block level to reduce congestion
  • Took responsibility for cleaning DRC/LVS/TIMING closure of block
  • Ran FEV on the block & resolved issues with noneq
  • Resolved timing issues by using Bounds & path groups
  • Fixed congestion issues by using placement blockages
  • Implemented clock push & pull to fix setup & hold violations
SynthesisFloorplanPlacement & RoutingCTSTiming AnalysisSignal Integrity+6

Altran

Software Engineer

Nov 2019Apr 2021 · 1 yr 5 mos · Bengaluru, Karnataka, India · Remote

C (Programming Language)

Education

New Horizon College of Engineering, BANGALORE

Bachelor of Engineering

Jan 2015Jan 2019

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