V

VEMALA SRAVANI

Software Engineer

Bengaluru, Karnataka, India3 yrs 7 mos experience

Key Highlights

  • Expert in SOC DFT verification methodologies.
  • Proficient in Synopsys tools for design verification.
  • Strong background in Verilog and SystemVerilog.
Stackforce AI infers this person is a semiconductor verification engineer with expertise in design for test methodologies.

Contact

Skills

Core Skills

Soc Dft VerificationSoc15 ArchitectureSynopsys ToolsVerilog

Other Skills

JTAG DFT VERIFICATIONRegression AnalysisCode CoverageSystemVerilogRegression TestingUVM RALIJTAGDigital LogicUnixI2CVHDLAssertion Based VerificationAXIJoint Test Action Group (JTAG)AMBA AHB

Experience

3 yrs 7 mos
Total Experience
1 yr 5 mos
Average Tenure
9 mos
Current Experience

Smartsoc solutions pvt ltd

DFX_DV Engineer

Jul 2025Present · 9 mos · Bengaluru, Karnataka, India · On-site

SOC DFT VERIFICATIONJTAG DFT VERIFICATION

Amd

DFX_DV Engineer

Jul 2025Present · 9 mos · Bengaluru, Karnataka, India · On-site

SOC15 ArchitectureRegression Analysis

Gaafet semiconductor pvt ltd

Design and Verification Engineer

Jun 2024Jun 2025 · 1 yr · Bengaluru, Karnataka, India · On-site

Synopsys toolsCode Coverage

Truescale technologies pvt ltd

Design and Verification Engineer

Jul 2022May 2024 · 1 yr 10 mos · Bengaluru, Karnataka, India · On-site

VerilogSystemVerilog

Education

Jawaharlal Nehru Technological University Kakinada (JNTUK)

B. Tech — Electronics and Communications Engineering

Jan 2019May 2022

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