jamshed alam

Software Engineer

India14 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in UVM and PCIe.

UvmPcieI2c

Assertion checkerFunctional coverageAssertionGPIOAVSBus VIPCode coverageSATANVMeShell scriptingSystemVerilogModelSimSynopsys toolsVerilogAlteraASIC

PCIe ,Nvme, I2C,AXI,APB

14 yrs 3 mos

Total Experience

9 yrs 10 mos

Average Tenure

14 yrs 3 mos

Current Experience

Dec 2018 – Present · 7 yrs 4 mos · India

1.Done IP Level Verification for UASC. (Done UVM Testbench development)
2.Done IP Level Verification for HTU(Developed UVM TestBench ) Including Assertion checker, functional covearge etc.

UVMPCIeAssertion checkerFunctional coverage

Dec 2017 – Present · 8 yrs 4 mos · Banglore

UVMPCIeAssertionFunctional Coverage

Jan 2017 – Present · 9 yrs 3 mos · Bengaluru Area, India

Project Accomplished at Moschip.
A) Worked for Maxim Integrated -
1 Developed Three UVM testbench from existing VIP for I2C,GPIO,AUX and encapsulated into one
env IOsub system
2.Developed AVSBus VIP(Master and Slave) and Testbench using UVM Based Methodology .
B)Worked for Synopsys on Code coverage for DMAC project.
C) Worked On SATA protocol for Implementing some VIP feature ,TestCases and Scoreboard

UVMI2CGPIOAVSBus VIPCode coverage

Jan 2012 – Present · 14 yrs 3 mos · Bhubaneshwar Area, India

Project Accomplished At PerfectVips
1.Developed PCIe TestPlane for TL,DL and PHY layer for Both PerfectVIPs and Synopsys in both in both ovm and uvm.
2.Developed Testcases for TL,DL(Individually implemented),PHY(Only LTSSM cases) for PerfectVIPs and Synopsys.
3Worked on testcase development of NVME Express,and integrated with PCIe..
4.Implemented Post Process PCIe Performance Parameter calculation using shell script.
5.Woked for the customer liker Altera and BRCAM through Synopsys .

PCIeUVMNVMeShell scripting