Jenish Radadiya — Software Engineer
Graduated in Electronics and Communication (B.Tech) from Birla Vishwakarma Mahavidyala Engineering College, Vallabh Vidyanagar, Anand Full dedication towards work. Design Verification Engineer with almost 4.5 years of relevant experience in ASIC Verification including definition and development of Verification Environment and testplan definition. Experience of working in System Verilog and UVM based Constrained Driven Verification Environment. Experience of working on complex protocols like PCIe-1.1, 2.0, 3.0, 4.0, 5.0, 6.0, CXL 2.0 and AHB. Good exposure on revision tracking tools like Perforce and SVN. Reach me out at : jenishradadiya80031@gmail.com
Stackforce AI infers this person is a skilled ASIC Verification Engineer with expertise in complex protocol verification.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 1 mo
Skills
- Asic Verification
- System Verilog
Career Highlights
- 4.5 years in ASIC Verification
- Expert in System Verilog and UVM
- Experience with complex protocols like PCIe and CXL
Work Experience
Synopsys Inc
Senior Engineer (2 yrs)
Asic Digital Design Engineer, II (1 yr 5 mos)
eInfochips (An Arrow Company)
ASIC Verification Engineer (1 yr 8 mos)
Project Trainee (2 mos)
eiTRA - eInfochips Training & Research Academy Ltd
Project Intern (8 mos)
Education
Bachelor of Technology - BTech at BIRLA VISHVAKARMA MAHA VIDHYLAYA(SFI), V.V.NAGAR 008
