Pooja Arora — Software Engineer
Physical Design Engineer with over 6 years of experience including 6 months of industrial training. Worked in 2 different organizations on technology nodes ranging from 5nm to 40nm. Good hands on floorplanning, place, CTS & Route in ASIC design tools such as EDI/FC and sign off tools such as tempus. Worked on block level timing and drc closure. Have worked on full chip floorplanning and special routing as well. Excellent experience in scripting languages like Perl, TCL and C-Shell.
Stackforce AI infers this person is a Physical Design Engineer with expertise in ASIC design and semiconductor technology.
Location: Noida, Uttar Pradesh, India
Experience: 7 yrs 8 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Over 6 years of experience in Physical Design Engineering.
- Expertise in ASIC design tools and methodologies.
- Proficient in scripting languages for automation.
Work Experience
Qualcomm
Lead Design Engineer -Sr (1 yr 8 mos)
NXP Semiconductors
Lead Design Engineer - PD (2 yrs 5 mos)
Soctronics
Engineer 2 (11 mos)
Physical Design Engineer 1 (1 yr 3 mos)
Physical Design Engineer (1 yr)
VEDA IIT
Physical Design Engineer (5 mos)
Education
Bachelor of Technology at Mahatma Jyotiba Phule Rohilkhand University
