Hrishikesh Kulkarni

Software Engineer

Noida, Uttar Pradesh, India6 yrs 5 mos experience

Key Highlights

  • 5 years of experience in synthesis and physical design.
  • Expert in static timing analysis and physical synthesis.
  • Currently a senior lead engineer at Qualcomm.
Stackforce AI infers this person is a semiconductor design expert with a focus on physical design and timing analysis.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Time ConstraintsPrimetimeTiming ClosureTimingPhysical SynthesisPlace & Route

About

5yrs Exp in SYNTHESIS, STA & PHYSICAL DESIGN

Experience

6 yrs 5 mos
Total Experience
2 yrs
Average Tenure
4 mos
Current Experience

Qualcomm

Senior Lead Engineer

Dec 2025 – Present · 4 mos · Noida, Uttar Pradesh, India · On-site

Time ConstraintsPrimetimeTiming ClosureTimingPhysical SynthesisStatic Timing Analysis+2

Stmicroelectronics

Technical Leader

Jan 2023 – Dec 2025 · 2 yrs 11 mos · Noida, Uttar Pradesh, India · On-site

PrimetimeTime ConstraintsStatic Timing Analysis

Adeptchip services private limited

Senior Physical Design Engineer

Aug 2020 – Jan 2023 · 2 yrs 5 mos · Bengaluru, Karnataka, India · On-site

PrimetimePhysical Design

L&t technology services

Physical Design Engineer

Jun 2019 – Mar 2020 · 9 mos · Bengaluru, Karnataka, India · On-site

PrimetimeStatic Timing Analysis

Rv-vlsi and embedded design centre

Trainee

Feb 2018 – Aug 2018 · 6 mos · Bengaluru, Karnataka, India · On-site

Place & RouteStatic Timing Analysis

Education

Global Academy Of Technology

Bachelor of Engineering - BE

Aug 2013 – Jun 2017

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