Himali Parikh

Software Engineer

India14 yrs 1 mo experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in SoC design at Intel Corporation.
  • Strong background in EDA tools and methodologies.
  • Proficient in CMOS and memory design techniques.
Stackforce AI infers this person is a semiconductor design engineer with expertise in EDA and SoC architecture.

Contact

LinkedIn

Skills

Other Skills

Cadence VirtuosoCMOSEDAVerilogSPICELogic Designmemory design

Experience

14 yrs 1 mo
Total Experience
7 yrs
Average Tenure
7 yrs 2 mos
Current Experience

Intel corporation

2 roles

Staff SoC Design Engineer

Promoted

Jul 2024 – Present · 1 yr 9 mos

SoC Design Engineer

Feb 2019 – Jul 2024 · 5 yrs 5 mos

Arm

3 roles

Senior Design Engineer

Promoted

Jul 2015 – Dec 2018 · 3 yrs 5 mos · San Jose, California

Design Engineer

Jan 2012 – Jul 2015 · 3 yrs 6 mos · San Jose, California

Memory Design Intern

Sep 2011 – Dec 2011 · 3 mos · San Jose, California

Education

San José State University

Master's degree — Electronics material and devices

Jan 2009 – Jan 2011

Stackforce found 100+ more professionals with Cadence Virtuoso & CMOS

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