Manoj Mohan

Software Engineer

Bengaluru, Karnataka, India11 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC and FPGA design and verification.
Proficient in physical design and timing analysis.
Experienced in software development for defense applications.

Stackforce AI infers this person is a Semiconductor and Defense industry specialist with expertise in ASIC design and software development.

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Skills

Core Skills

Asic DesignPhysical DesignSoftware Development

Other Skills

Floating Point DesignFused Multiply Add (FMA)Floor-planningTiming AnalysisAtopTechPrimeTimeCommunication SystemsLabViewC++VHDLSystem VerilogNI LabVIEWSynopsys PrimetimeCadence VirtuosoCadence Encounter

About

- Actively seeking full-time opportunities in the fields of Digital IC/ASIC/FPGA Design/Verification, Memory Design, Physical Design or Computer Architecture. - Graduate Student in Electrical Engineering at The University of Texas at Dallas Technical Exposure: Programming Languages : C, Embedded C, C++, LabView, MatLab Scripting Languages - Shell, Perl, TCL Assembly Level Programming IDE : Keil µVision, Code Composer Studio HDL : Verilog, VHDL, System Verilog Synthesis Tools : Xilinx, RTL Compiler, Design Compiler, Quartus Layout Tools : Cadence Virtuoso Place and Route Tool : Cadence Encounter, AtopTech Physical Verification Tools: Cadence Assura Parasitics Extraction Tools: Cadence Quantus RC, Synopsys StarRC Static Timing Analysis : Primetime Verification Tool : Cadence Encounter Test ATPG : Tetramax Simulation Tool : Modelsim, HSPICE Operating Systems : Windows, UNIX

Experience

11 yrs 8 mos

Total Experience

3 yrs 10 mos

Average Tenure

8 yrs 8 mos

Current Experience

Mediatek

Engineer

Aug 2017 – Present · 8 yrs 8 mos · Bengaluru, Karnataka, India

Ssr labs

ASIC Design Engineer

Nov 2016 – Feb 2017 · 3 mos · San Francisco Bay Area

Worked on the design of Mantissa Multiplier for Quadraple precision Floating Point for Fused Multiply Add (FMA) unit

ASIC DesignFloating Point DesignFused Multiply Add (FMA)

Broadcom limited

IC Design Intern

Aug 2015 – Dec 2015 · 4 mos · San Francisco Bay Area

Worked as an IC Design Intern in Broadcom’s ING division for the physical design team, which involves working on block level build starting from floor-planning and taking it through release, fix block level DRC’s/ECO’s for fixing the timing issues.
I have had the responsibility in owning blocks and worked on 16nm FinFET Technology nodes. I was required to be able to start from floorplanning to PnR, establish timing constraints, review timing reports, and physically close timing at the block level.
Worked on the physical design of the block which are part of highly complex network switching chips. Blocks instances run to 2 million cells and hundreds of macros.
AtopTech: This tool is used in taking the synthesised netlist starting from the floorplanning to the PnR
Tweaker: This tool is used in doing hold and setup timing fixes for various corners. It is also used for fixing violations related to noise/cap/transition after release
Timing: PrimeTime is the STA tools used for sign off in evaluating the timing of the design and also the reports were evaluated for timing fixes.

Physical DesignFloor-planningTiming Analysis

Bharat electronics

Deputy Engineer

Sep 2011 – Jun 2014 · 2 yrs 9 mos · Bengaluru Area, India

Software development of application software of Communication Systems for Indian Naval Ships and Submarines using Qt Programmer.
Design and Development of Interface and Switching Board of Remote Communication Terminals.
Developed the simulator of the communication protocol of Radio Receiver EK896 from Rohde and Schwarz and MSK Demodulator from NSG Datacom in Lab View.
Designed and developed an automated test suite to perform Acceptance Test for PC104 Board for the integrated product using LabView.
Providing technical support in on-board testing of application software, radios and communication system in Indian Naval Ships and Submarines.

Software DevelopmentCommunication SystemsLabView