Raghav Sharma

Software Engineer

Bengaluru, Karnataka, India3 yrs 2 mos experience

AI EnabledAI ML Practitioner

Key Highlights

Expertise in ASIC implementation and memory design.
Strong background in circuit characterization and validation.
Experience in mentoring and guiding memory design projects.

Stackforce AI infers this person is a semiconductor design engineer with a focus on ASIC and memory design.

Contact

Skills

Core Skills

Asic ImplementationMemory DesignIn-memory Compute

Other Skills

PVT-aware circuit characterizationBitcell analysisMemory Architectural tiling validationMemory design conceptsGuiding design projectsMentoringMemory design projectsAI accelerator implementationPrime powerSynopsys Design CompilerPhysical DesignLogic SynthesisDFTvcsSynopsys tools

About

I hold a Master’s degree in ECE (VLSI) from IIIT Delhi, with strong fundamentals across digital and analog circuits, memory design, ASIC implementation, and solid-state physics, built to reason about silicon from first principles. My experience spans SRAM design, standard cell development, RTL-to-GDS implementation, PVT-aware circuit characterization. I also worked on in-memory compute research at STMicroelectronics, exploring architectural and circuit-level trade-offs in accelerator designs. I’m drawn to custom silicon problems at the intersection of circuits, timing, and architecture, where correctness, margin, and simplicity matter. I’m self-driven, enjoy learning continuously, and take ownership of ambiguous, high-impact challenges. I currently work as an Engineer in the Global Circuits team at NVIDIA, Bangalore.

Experience

3 yrs 2 mos

Total Experience

1 yr 4 mos

Average Tenure

6 mos

Current Experience

Nvidia

ASIC Engineer

Oct 2025 – Present · 6 mos · Bengaluru, Karnataka, India · Hybrid

Global Circuits team

ASIC implementationmemory designPVT-aware circuit characterization

Synopsys inc

5 roles

Senior Engineer

Feb 2025 – Oct 2025 · 8 mos

Senior Engineer

Promoted

Feb 2025 – Oct 2025 · 8 mos

RnD Engineer 1

Jul 2023 – Feb 2025 · 1 yr 7 mos

Bitcell analysis
Memory Architectural tiling validation: HS1PRF, HD1P Memory compilers
Design

Bitcell analysisMemory Architectural tiling validationmemory design

RnD Engineer Memory Design Intern

Jan 2023 – Jun 2023 · 5 mos

Memory Design Intern

Memory Design Intern

Jan 2023 – Jun 2023 · 5 mos

Indraprastha institute of information technology, delhi

Memory Design & Test Teaching Assistant (Voluntarily)

Jan 2025 – Oct 2025 · 9 mos · Delhi, India

Engaged as TA for the Memory Design &Test course at IIIT Delhi.
Helping student understand memory design concept, guiding in design projects.

Indraprastha institute of information technology, delhi

Teaching Assistant

Jan 2023 – May 2023 · 4 mos · Delhi, India · Hybrid

Memory Design & Test.
Mentoring M.Tech students on Memory design projects like Bitcell array, sense amplifier, replica path, In-memory compute etc.
Focus is on robust designs by qualifying for different PVT's, Monte Carlo 6-sigma qualification. Low power designs & assist schemes are also explored.

Memory design conceptsGuiding design projectsmemory design

Stmicroelectronics

College Program Intern

Jul 2022 – Dec 2022 · 5 mos · Greater Noida · Hybrid

Worked on In-Memory Compute based AI accelerator implementation in the TRD group.

MentoringMemory design projectsmemory design

Bharat electronics limited

2 roles

Summer Intern

Jun 2018 – Aug 2018 · 2 mos · Ghaziabad, Uttar Pradesh, India

In-Memory ComputeAI accelerator implementation

Summer Trainee

Jun 2017 – Aug 2017 · 2 mos · Site 4, Sahibabad Industrial Area, Sahibabad, Ghaziabad, Uttar Pradesh 201010

Electronic regional test laboratory

Summer Trainee

Jun 2018 – Jul 2018 · 1 mo · Delhi, India

Defence research and development laboratory (drdl) - drdo

Summer Trainee

Jun 2017 – Jul 2017 · 1 mo · Lucknow Road, Timarpur, Delhi - 110 054

Worked on Project titled " Direction of Arrival estimation of an Acoustic (underwater) signal using Triplet Hydrophone (conventional) configuration at 5KHz and simulation of directivity DOA application in MATLAB " under emminent scientists in the Hydrophone division,SSPL.