GOPI REDDY CHAGANTI — Intern
An Electronics and Instrumentation Engineering graduate and VLSI Engineer with hands-on experience in RTL design and Verification. Proficient in RTL Design constructs and IP-level verification through UVM TB, assertions, constrained random, coverage-driven methodologies. I have worked on projects including interface protocols (AMBA AHB and APB), UART Verification and Router 2x3 Design and Verification. I look forward to contributing in collaborative environment that fosters learning and professional growth.
Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in digital electronics and verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 0 mo
Skills
- Verilog
Career Highlights
- Hands-on experience in RTL design and verification.
- Proficient in UVM TB and coverage-driven methodologies.
- Worked on multiple interface protocol verification projects.
Work Experience
MediaTek
VLSI Design Verification Apprentice (9 mos)
Maven Silicon
ASIC Design and Verification Trainee (1 yr 3 mos)
Education
Bachelor of Technology - BTech at Bapatla Engineering College
