Vinay kumar Maddala — Software Engineer

Senior RTL Design Engineer | 13+ Years in ASIC/FPGA Design & Verification Accomplished ASIC/FPGA design engineer with expertise in micro architecture, RTL design, verification, and integration for memory controllers, 5G/NR, RISC-V processors, and cryptographic systems. Proven track record of leading cross-functional teams to deliver high-performance, low-power solutions for enterprise and data center applications. Proficient in SystemVerilog, Verilog, and Bluespec, with hands-on experience in EDA tools (Cadence, Synopsys) and FPGA platforms (Xilinx, Intel). Recognized with Samsung spot Award for excellence in performance.

Stackforce AI infers this person is a seasoned ASIC/FPGA design engineer specializing in high-performance, low-power solutions for enterprise applications.

Location: Bengaluru, Karnataka, India

Experience: 13 yrs 6 mos