Rajeev Chauhan — Product Engineer
Enthusiastic entry-level member of the RTL Design Team with a focus on RTL writing, power benchmarking, and design automation using Python and TCL scripting. Actively involved in projects related to PolarFire SoC and PolarFire FPGAs, gaining proficiency in these areas. Conducted comprehensive studies to understand their architectures, contributing to optimized design strategies.
Stackforce AI infers this person is a VLSI Design Engineer with a focus on FPGA technologies.
Location: Saharanpur, Uttar Pradesh, India
Experience: 1 yr
Skills
- Sta
- System On A Chip (soc)
Career Highlights
- Proficient in RTL design and automation.
- Hands-on experience with PolarFire SoC and FPGAs.
- Strong foundation in VLSI design principles.
Work Experience
AMD
Design Engineer( contract) (1 yr)
Microchip Technology Inc.
Intern for FPGA Design (1 yr)
Education
M.tech at National Institute of Technology, Kurukshetra, Haryana
B.tech at Kurukshetra University
VLSI DESIGN at National Institute of Technology, Kurukshetra, Haryana
