Heerak Bandopadhyay

Associate Partner

Bengaluru, Karnataka, India19 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Senior Department Manager with extensive ASIC and SoC expertise.
Proven track record in power integrity for low-power designs.
Hands-on experience in advanced VLSI design methodologies.

Stackforce AI infers this person is a VLSI and ASIC design expert with a focus on power integrity in semiconductor industry.

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Skills

Core Skills

AsicSocPower IntegrityPower Analysis

Other Skills

Static Timing AnalysisPhysical DesignPrimetimeVLSIEDALogic SynthesisLow-power DesignVerilogTCLTiming ClosureIntegrated Circuit DesignFloorplanningCMOSSemiconductorsIC

Experience

19 yrs 5 mos

Total Experience

3 yrs 10 mos

Average Tenure

8 yrs 5 mos

Current Experience

Mediatek

2 roles

Senior Department Manager

Promoted

Oct 2021 – Present · 4 yrs 6 mos

Static Timing AnalysisASICPhysical DesignSoCPrimetimeVLSI+16

Senior Staff Engineer

Nov 2017 – Nov 2021 · 4 yrs

Intel corporation

SoC Design Engineer

Nov 2014 – Nov 2017 · 3 yrs

Lsi corporation

Engineer Senior

Jan 2013 – Nov 2014 · 1 yr 10 mos · Pune Area, India

Stmicroelectronics

3 roles

Technical Lead

Nov 2012 – Dec 2012 · 1 mo

have worked in Power Integrity of a project targeted for gaming by our client.

Sr. Design Engineer

Promoted

Oct 2010 – Nov 2012 · 2 yrs 1 mo

work domain includes:
> power integrity and other Signoff aspects at full chip level in 32nm & 28nm FDSOI Designs for low power hand held devices.

Design Engineer 1

Aug 2007 – Sep 2010 · 3 yrs 1 mo

work domain includes:
> power integrity aspects at full chip level in 32nm & 28nm FDSOI Designs for low power hand held devices.
> Certifying libraries/Kits as Design Package complaint.
Complete RTL2GDS flow in CADENCE SYNOPSYS etc platforms. & performing STA, Synthesis, PnR, Verification (DRC/LVS), on latest technology node :90nm, 65nm, 45nm, 32nm ..