Vishal Kumar — Software Engineer

Current Responsibilities:-► ATPG pattern generation, pattern retargeting, verification and optimum coverage analysis for Stuck-at, At-speed, Cell-aware and IDDQ faults.► Coordinate with DFT RTL & DFT verify team to implement ATPG test that drives high-quality tests and reduces DPPM.► Hierarchical/ flat Scan insertion with a minimum area overhead.► Generate and verify scan initialization sequence for ATPG usage. Verify in VCS simulation and Verdi waveforms.► Support Silicon by bringing up activities for the scan test and further debugging for the Sort & Class test.► Responsible for reporting test coverage and quality metrics.DFT experience includes:- • DFT Methodology and flow development along with practical experience in industry-standard EDA tools like Siemens (Mentor Graphics)'s Tessent, TestKompress, PrimeTime and Synopsys VCS and Verdi.• Possess knowledge of flow automation in scripting languages like TCL/python for efficient DFT activities on complex projects.Completed Master's degree focused on VLSI Design from Dr. B R Ambedkar National Institute of Technology Jalandhar. I am skilled in Digital Design, Design for testability (DFT), and SoC architecture. Possess sound knowledge of VLSI/ASIC design flow. Strong analytical and communication skills.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in DFT and ASIC methodologies.

Location: Bengaluru, Karnataka, India

Experience: 5 yrs 6 mos