Jan 2023 – May 2025 · 2 yrs 4 mos · Bengaluru, Karnataka, India · Remote

Aug 2022 – Dec 2022 · 4 mos · Shanghai, China

• SOC Verification Consultant , Client : AMD Shanghai, China
• (Employee of NexuxCorp Ltd, HongKong)
• Responsibility:
• > OSSIP, SDMA deployment and verification at various tablet, PC, server, mobile APU/dGPU SOCs for last 4 years.
• > Owned the responsibility of the IP deployment and verification and leading it for various project over last 3 years of work span along with initial 1 year of co-ownership.
• > Understand IP and SOC micro architecture specification, refine the test plan to align with project specific features added/removed.
• > Review Test plan with internal team and external testplan review with SOC architect.
• > good understanding of IP integration flow and SOC design flow to exercise SOC level verification of integrated IP.
• > Bring-up of the sanities in initial milestone and followed the integration and DV scheduled milestones with respect to completion of verification of IP.
• > Debugged the failed tests with Verdi for design issues, tried to find out exact root cause of issues.
• > Work on functional/code coverage closure, write SoC point view covergroups to cover all design spec and features andwrite SVA property to include in functional coverage.
• > Write toggle coverage for OSSIP interface and analyse the coverage , write extra directed tests to cover holes.
• > Worked on writing assertion checkers in SV and bind it with RTL design, use the DPI to communicate with C based tests
• >At various stages of project execution, run logical equivalence check LEC to make sure correct RTL exists between IP depot and SOC depot.
• > Run batch regression for test cases suite and debugging it. enabled the coverage and analyse coverage results
• > Developed the perl script to collect the regression failure with each error signature.
• > Gained hands on experience on EDA tools for simulation and waveform debug, formality LEC,

Dec 2021 – Jul 2022 · 7 mos · Shanghai, China

• SOC Verification Consultant , Client : AMD Shanghai, China
• (Employee of SiconTech (Shanghai) design Ltd, subsidiaries of Capgemini Engineering, Shanghai, China)

Dec 2018 – Nov 2021 · 2 yrs 11 mos · Shanghai, China

• SOC Verification Consultant , Client : AMD Shanghai, China
• (Employee of SiconTech (Shanghai) Design Ltd, Subsidiaries of Capgemini Engineering, Shanghai, China)
• > Owned full responsibility of SOC verification of OSSIP in various projects.
• > Aligned with project SOC DV team for Testplan reviews and to meet different milestones requirements,
• and weekly syncup with SOC team to provide the status of IP deployment and capture the progress of SOC.
• > Deployment and verification of Operating System Support (OSS) subsystem (includes Host Data Path
• (HDP) gateway from host CPU to local frame buffer memory , interrupt collection and reporting to
• generate interrupt to system (interrupt handler IH) and Semaphore synchronizer block) at AMD's
• various next generation GPU integrated APU and discrete GPU SOCs.
• > SOC level Verification of System DMA module in memory controller subsystem to access mem over
• different datapaths from SDMA to sysmem and local DRAM memory
• > Simulation of tests suite and debugging of failed tests, gained the good exposure to Synopsys VCS
• and Verdi tool for waveform and coverage collection and reports.
• > Hands on experience on functional coverage and code coverage closure , write the coverage
• covergroups to cover transition( toggle ) coverage of OSSIP interface at SOC and redevelop tests or
• write directed tests for coverage holes.
• >Hands on experience with logical equivalence check (LEC) to check RTL mismatch between IP depot
• RTL and SOC depot RTL for OSSIP with Synopsys Formality fm_shell tool setup.
• >Provided support for performance verification developed the perl script to trace the time consumed by data traffic and generate PV report.

Jan 2017 – Nov 2018 · 1 yr 10 mos · Hyderabad, India

• IP/SOC Verification Consultant, Client: INEDA SYSTEMS Hyderabad, India (Jan. 2017 - Nov. 2018 )
• (Employee of Chipsolve Technologies, Hyderabad, India )
• 1. SOC level verification of Pulse width modulation IP
• > Understanding of automotive SOC architecture and usage of PWM IP at SOC.
• > Understood the IP specs/features and interfaces to integrate IP to SOC and developed a testplan
• exercise SOC level verification.
• > Created all the C++ based testscases from scratch and gained good understanding simulation and RTL
• debug. Tools: ncsim simulator and SimVision waveform dumper.
• > Developed SVA checkers from scratch to cover the each testcase feature and triggered the assertion
• coverage properties. Analyzed the assertion coverage, found the corner scenarios to verify.
• > Run the Gate level simulation (GLS) of couple of tests for unit delay and zero delay.
• 2. PWM design verification.
• > PWM module RTL design verification based on UVM methodology
• > Understood the existing coverage driven IP verification SV testbench and refined the testcases to
• generate optimistic stimulus for coverage closure.
• > Gained good exposure of functional coverage and code coverage. added covergroups/coverpoints
• to partially completed coverage model.
• > Collected and merged functional coverage and analyzed the coverage report with IMC tool.
• 3. Verification of Clock frequency deviation monitor (CFDM) IP at SOC
• > As SOC contains the multiple clock domains drives the various clocks with different frequencies to
• specific IP's clocks and system clocks.
• > Simulated testscases for all clocks frequency precision checking with rest of the clocks as reference
• 4. Pinmux bench to verify design connectivity and IO pad mux
• > To minimize the area on chip, dedicated IO pads count is reduced, instead selected multiple IO ports
• on single IO pad cell.
• > Developed the perl script to add system verilog assertions in pinmux bench to verify correct IO
• selected on IO Pad cell.

Jul 2016 – Dec 2016 · 5 mos · Bengaluru, India

• Design verification Intern
• > Learnt verilog, SV and UVM methodology concepts
• > worked on basic RTL design module synchronous/asynchronous FIFO and verify it by SV testbench
• > learnt ARM protocols APB, AHB, AXI and excercise the UVM flow to verify it.
• > learnt about UART and created C based testscase to verify block at dummy SOC environment

Oct 2013 – Feb 2014 · 4 mos