sabarathnam Ekambaram

Software Engineer

Hyderabad, Telangana, India17 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

15+ years of VLSI industry experience.
Expertise in High-Speed Analog and Mixed-Signal Designs.
Strong focus on innovation and automation in IO development.

Stackforce AI infers this person is a VLSI design expert with a focus on high-speed analog and mixed-signal technologies.

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Skills

Core Skills

Mixed SignalVlsiAnalog

Other Skills

PCIeTx EqualizerSerDes Development(LP)DDR2/3 IO DevelopmentUltra Low Cost IO DesignLow Power IO DesignLVDS TX DevelopmentCharacterization Tool DevelopmentMEMS Accelerometer ControlDesign AutomationPost Silicon TestingSignal Integrity AnalysisMixed Signal VerificationGPIO DesignAMS Verification

About

* 15+ years of VLSI industry experience with expertise in IO High-Speed Analog and Mixed-Signal Designs with expertise in memory interfaces Variants: (LP)DDR3/4/5 @4.266Gbps, HBM2e/3 @8Gbps, UCIE @8Gbps, Fully differential Tx and Rx with equalizations (TX FFE, Rx CTLE etc) , Flavors of LVCMOS combo’s (including overvoltage drive (3.3V to 1.8V) & failsafe tolerance), Crystal Oscillator & POR receivers * Circuit Lead for Tx/Clocking designs and interface for Timing, PHY, SIPI, VnC and ESD Teams in multiple projects. * Hands-on post silicon Characterization for High Speed IO's across multiple generations * Bent for innovation and automation in complete IO development cycle * System Modeling with Matlab / Scilab * Demonstrated high ownership/accountability with strong focus on continuous learning / development.

Experience

17 yrs 8 mos

Total Experience

8 yrs 10 mos

Average Tenure

12 yrs 7 mos

Current Experience

Amd

2 roles

Principal Member of Technical Staff

Promoted

Jul 2025 – Present · 10 mos

Senior Member of Technical Staff

Oct 2013 – Jul 2025 · 11 yrs 9 mos

Sankalp semiconductor private limited

3 roles

Design Team Lead

Oct 2012 – Sep 2013 · 11 mos

PCIe Gen 2 Tx Equalizer & serdes development -- 2.5 & 5 Gtps
(LP)DDR2/3 IO develoment (On contract to LSI India)

PCIeTx EqualizerSerDes Development(LP)DDR2/3 IO DevelopmentMixed SignalVLSI

Lead Design Engineer

Promoted

Sep 2011 – Sep 2012 · 1 yr

Design of Ultra low cost and low power IO's. (On contract to Texas Instruments for MSP430 Microcontroller)
LVDS TX development 40nm
Characterisation tool development for dotlibs using perl

Ultra Low Cost IO DesignLow Power IO DesignLVDS TX DevelopmentCharacterization Tool DevelopmentAnalogVLSI

Design Engineer

Jul 2008 – Sep 2011 · 3 yrs 2 mos

Closed loop control of MEMS Accelerometer (Matlab Modeling and System Design )
Design Automation of Lvcmos18 IO
Design of Lvcmos3.3V/2.5V using 1.8V devices (Architecture,Design and Verification) (On contract to PMC Sierra India)
Post silicon testing of Lvcmos18 IO using HP83K Tester (For PMC Sierra Canada)
Sigal Integrity Analysis for DDR2 IO
Mixed signal verification of Bluetooth and WLAN

MEMS Accelerometer ControlDesign AutomationPost Silicon TestingSignal Integrity AnalysisMixed Signal VerificationVLSI+1