V

Venkatesh Vasudevan

CTO

Bengaluru, Karnataka, India16 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in modeling neural network architectures.
  • Proven leadership in semiconductor technology upgrades.
  • Strong background in integrated circuit design.
Stackforce AI infers this person is a Semiconductor and AI specialist with a focus on embedded systems.

Contact

Skills

Core Skills

Embedded SystemsIntegrated Circuit Design

Other Skills

CRequirements AnalysisSimulationsAnalogMixed SignalFPGASoCC++VerilogXilinxVLSIASICVHDLSemiconductorsEDA

About

Modeling Green Neural Network Architecture for Speech Processing and integrating it as PCI device and Embed Mode Device.

Experience

16 yrs 11 mos
Total Experience
2 yrs 5 mos
Average Tenure
7 yrs 11 mos
Current Experience

Intel corporation

Senior Technical Manager

Jun 2018Present · 7 yrs 11 mos · Bangalore

  • Current:
  • Leading team for following:
  • Upgradation of PCIe ver 3.0 compliant Virtual Test Card to PCIe ver 5.0 compliant Virtual Test Card.
  • Modeling in Device Modeling Language (DML) on Wind River Simics
  • Test Cases in Python
  • Completed: Modeling Intel Deep Neural Network Module and Gaussian Mixture Model for Speech Processing IP. Modeling in SystemC and C++.
CRequirements AnalysisSimulationsIntegrated Circuit DesignAnalogMixed Signal+14

Test and verification solutions

Manager SystemC Modeling

Aug 2014May 2018 · 3 yrs 9 mos · Greater Bengaluru Area

  • Manager SystemC Modeling for projects at LG Electronics, NXP Semiconductor, Blu-Wireless and ST-Microelectronics

Spel semiconductor

Manager, IC Design

Sep 2012May 2014 · 1 yr 8 mos · Chennai

  • Managed SystemC code development for H.264 Video Codec

Cognizant technology solutions

Researcher

Sep 2010Oct 2012 · 2 yrs 1 mo · Greater Chennai Area

  • Team Lead of Verification Team.
  • Our Team verified a complex FPGA based Design in SystemC

Conexant

Senior Design Engineer

Jul 2005Jan 2006 · 6 mos · Pune/Pimpri-Chinchwad Area

  • Design and Verification of GPON IP Core blocks.
  • As part of the Design and Verification Teams, developed the Framer and verified the Reed-Solomon Error Correction Module in C++

Siemens

Hardware Development Engineer

Jan 2005Jun 2005 · 5 mos · Pune/Pimpri-Chinchwad Area

  • Part of the Image Processing Development Team.
  • Implemented embedded C/C++ code (Xilinx PowerPC) for Video Processing, Display Processing and control of Image Processing Hardware.

International institute of information technology

Research Associate

Apr 2004Dec 2004 · 8 mos · Pune/Pimpri-Chinchwad Area

  • Lecturer in C/C++ and Digital Design.

Education

The University of Queensland

PhD — Fault Tolerant Digital Design

Jan 2006Jan 2009

Griffith University

Master of Engineering VLSI — VLSI

Jan 2003Jan 2003

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