dileep gangavaram

Software Engineer

Bengaluru, Karnataka, India14 yrs 10 mos experience

Most Likely To SwitchAI Enabled

Key Highlights

Expert in Power Estimation and Electromigration.
Proficient in Low-power Design and Electronic Circuits.
Experienced in standard cell characterization for advanced technologies.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and low-power design methodologies.

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Skills

Core Skills

Power EstimationPower DeliveryElectromigrationLow-power Design

Other Skills

Liberty Variation Format (LVF) generationAOCV methodology debuggingStandard cell extraction and characterizationDebugging of PDK transistor model filesPrime TimeAOCV methodologyStandard cell extractionCharacterizationLiberateSilicon smartElectronic CircuitsTransistorsOptimization TechniquesPower ConsumptionOptimization

Experience

14 yrs 10 mos

Total Experience

3 yrs 1 mo

Average Tenure

5 yrs 8 mos

Current Experience

Intel corporation

SDE

Sep 2020 – Present · 5 yrs 8 mos · Bengaluru, Karnataka, India

Power EstimationElectromigration

Lakshsemi

Senior Physical Design Engineer

Sep 2019 – Sep 2020 · 1 yr · Bengaluru, Karnataka, India

Invecas

Senior Consulting Engineer (consultant to Invecas)

Oct 2014 – Sep 2019 · 4 yrs 11 mos · Hyderabad Area, India

Liberty Variation Format (LVF) generation with Liberate (cadence) and validation through Prime Time (prime time).
AOCV , methodology debugging and releases for 14nm technology with monte carlo in silicon smart.
Standard cell extraction and characterization and view generation like AOCV for 14nm(FinFET) and 22nm(FDSOI) through liberate(cadence) and silicon smart
Debugging of PDK transistor model files (14nm FinFET and 22FDX) analyzing the effect of local variations

Liberty Variation Format (LVF) generationAOCV methodology debuggingStandard cell extraction and characterizationDebugging of PDK transistor model filesPower DeliveryElectromigration

Ineda systems

2 roles

Physical Design Engineer (consultant to Ineda)

Oct 2013 – Oct 2014 · 1 yr · Hyderabad Area, India

Handled tile level PnR in 28nm – Floor planing, placement, CTS, Routing, Bump planing and Routing and IO ring Implementation.
Handled block level BUMP planing and Bump routing and IO ring Implementation.

Low-power DesignElectronic Circuits

Physical Design Engineer (Intern)

Jul 2012 – Oct 2013 · 1 yr 3 mos · Hyderabad Area, India

Have a good exposure for the standard cell characterization methodology development for 28nm.
Mainly involved in the development of NLDM library generation.

Transistors