Prateek Pendyala — Software Engineer
Physical Design & On Die Electrical Analysis Engineer with rich experience in planning, designing & and analysing power delivery networks. Proven track record of successful power integrity execution on SOC tape-outs (Client, Server, SOC, NSP, Smartphone, Wi-Fi7, IOT & Test Chip) Emphasis on Static, Dynamic IR, Electromigration, ESD, Bump and wire bond planning & RDL routing, IO IR, Jitter& Vmin analysis. Experience with developing and testing power integrity analysis methodologies intersecting with static timing analysis(STA), Physical design, physical verification and PPA improvement. Skilled in Perl, Python3 and TCL languages. Tool proficiency in Redhawk, Redhawk-SC, Voltus, Innovus, Primetime, ICC2 & SPICE simulation.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Power Integrity.
Experience: 10 yrs 1 mo
Skills
- Physical Design
- Power Integrity
Career Highlights
- Expert in power integrity execution on SOC tape-outs.
- Skilled in multiple scripting languages including Python and Perl.
- Strong background in physical design and power delivery networks.
Work Experience
Silicon Physical Design Engineer, PG Grid Methodology (2 yrs 6 mos)
MediaTek
Staff Engineer (1 yr 8 mos)
Qualcomm
Senior Engineer (2 yrs)
Intel Corporation
SoC Design Engineer (3 yrs 11 mos)
Education
PG in Advanced VLSI Chip Design at Indian Institute of Science (IISc)
Master of Science by Research at International Institute of Information Technology Hyderabad (IIITH)
Bachelor of Engineering - BE at Nagpur University
