Vineet Kumar

Software Engineer

Delhi, India12 yrs 3 mos experience
Highly Stable

Key Highlights

  • Expert in low-power design methodologies.
  • Strong background in logic synthesis and power estimation.
  • Proven track record at leading tech companies.
Stackforce AI infers this person is a semiconductor design expert with a focus on low-power solutions.

Contact

LinkedIn

Skills

Other Skills

LECCLPPower EstimationCPFUPFLow-power DesignLogic Synthesis

Experience

12 yrs 3 mos
Total Experience
4 yrs 1 mo
Average Tenure
--
Current Experience

Qualcomm

2 roles

Staff Engineer

Promoted

Dec 2021 – Jan 2024 · 2 yrs 1 mo

Sr Lead Engineer

Jul 2018 – Nov 2021 · 3 yrs 4 mos

Cadence design systems

3 roles

Lead Product Validation Engineer

Promoted

Jan 2017 – Jul 2018 · 1 yr 6 mos

Product Validation Engineer - II

Promoted

Jul 2014 – Dec 2016 · 2 yrs 5 mos

Software Engineer

Nov 2012 – Jul 2014 · 1 yr 8 mos

Texas instruments

Digital Design Engineer

Jul 2011 – Oct 2012 · 1 yr 3 mos · Bangalore

  • Power Design Integrity.

Education

Netaji Subhas Institute of Technology

Bachelor of Engineering (BE)

Jan 2007 – Jan 2011

S.M.Arya Public School

AISSCE — Science

Jan 2005 – Jan 2007

Stackforce found 100+ more professionals with LEC & CLP

Explore similar profiles based on matching skills and experience

Ankush Chaudhary

Ankush Chaudhary

Senior Engineer

at MediaTek

Wardha, India2 yrs 9 mos exp
Application-Specific Integrated Circuits (ASIC)Synthesis
Ashwin Ramamurthy

Ashwin Ramamurthy

Senior Staff Engineer

at MediaTek

Bengaluru, India9 yrs 8 mos exp
SynthesisApplication EngineeringPower AnalysisMethodology Development
Naveen Kumar T V

Naveen Kumar T V

Staff physical design Engineer

at MediaTek

Bangalore Urban, India7 yrs 11 mos exp
Physical DesignTiming ClosurePhysical Verification
Utsasarit Dutta

Utsasarit Dutta

Synthesis and STA Engineer

at MediaTek

Bengaluru, India2 yrs 9 mos exp
Static Timing Analysis
Hema Lakshmi Singana

Hema Lakshmi Singana

Synthesis Engineer

at MediaTek

Bengaluru, India5 yrs 4 mos exp
Physical DesignSynthesis
Deeksha Tiwari

Deeksha Tiwari

SoC Design Intern

at Intel Corporation

Gurgaon, India0 mo exp
VLSI Physical Design
Sabu Swaroop

Sabu Swaroop

Staff Engineer

at Qualcomm

Bengaluru, India13 yrs 10 mos exp
Low-power DesignASICFormal VerificationLogic Synthesis
Anandhan M

Anandhan M

Sr. Manager

at AMD

Bengaluru, India19 yrs 3 mos exp
Low-power Design