Tapodyuti Mandal

Software Engineer

Hyderabad, Telangana, India21 yrs 5 mos experience
Highly Stable

Key Highlights

  • 20+ years in EDA tool development.
  • Led Vivado Simulator development team.
  • Expert in System Verilog and UVM implementation.
Stackforce AI infers this person is a leader in EDA tools with a focus on HDL simulation and performance optimization.

Contact

Skills

Core Skills

Hdl SimulationSystem VerilogTeam ManagementC/c++Dft ToolsStatic Timing AnalysisParser Development

Other Skills

UVMPerformance ImprovementIPC ToolsC++LexYaccSimulationsCompilersDesign PatternsField-Programmable Gate Arrays (FPGA)VerilogSoftware Development

About

Experienced software professional with 20+ years of experience in the EDA tool development. Currently working as Senior Manager at Xilinx and leading the Vivado Simulator (also known as XSIM) India development team. XSIM is a license free software with capabilities similar to other licensed HDL simulators in the EDA world. Key accomplishments include : - Implementing the System Verilog language features Leading the implementation of various complex features such as Class, Virtual Function, Constraint Random, Coverage, Program Block, Clocking Block, Streaming Opertaors, Array Methods etc. - Enablement the UVM features for verification Driving the UVM Enablement initiative. All UVM example designs from Accellera, Dulous and Verification Academy are successfully ported in XSim. - Improve Elaboration and Simulation Performance to match with the standard simulators from other vendors. - LLVM IR generation and optimization for smaller and efficient object code. This is an ongoing project where during elaboration a more properietary and custom IR is generated and that is later transformed into LLVM IR. - Enabling Hardware-in-loop simulation where preverified hardware blocks are placed on the FPGA boards and under development blocks and testbenches are simulated in the standard HDL simulator kernel. - Build the Simulator India development team. Hiring, Coaching and Mentoring a bunch of young and fresh engineers and helping them to grow in a competitive environment. Also had prior experience in working various other EDA tools like Static Timing Analysis, Synthesis, Language Parser, Compiler. Highly proficient in C++, Design Patterns, STL.

Experience

21 yrs 5 mos
Total Experience
8 yrs 9 mos
Average Tenure
3 yrs 10 mos
Current Experience

Amd

Principal Engineer

Jul 2022Present · 3 yrs 10 mos · Hyderabad, Telangana, India

Xilinx

2 roles

Senior Manager

Jul 2017Jun 2022 · 4 yrs 11 mos · Hyderabad, Telangana, India

  • Implementing the System Verilog language constructs into the Vivado Simulator tool which is an RTL simulation tool for Verilog, VHDL, System Verilog and SystemC. Leading the simulator development team at Xilinx Hyderabad and productize the UVM features in the simulator.
  • Involved in improving simulator performance to match with the industry standard simulators.
System VerilogUVMHDL SimulationPerformance Improvement

Software Engineering Manager

Nov 2012Jun 2017 · 4 yrs 7 mos · Hyderabad, Telangana, India

  • Leading the Vivado Simulator team responsible for Implementation of various System Verilog features from scratch.
  • Implemented and pioneered various performance improvement ideas for improving the speed and memory footprint of the HDL simulator tool.
  • Hire and Coach individual engineers to make them productive.
System VerilogPerformance ImprovementTeam ManagementHDL Simulation

Interra systems

3 roles

Manager

Jul 2008Oct 2012 · 4 yrs 3 mos · Kolkata Area, India

  • Managing the ODC for Texas Instruments developing a set of tools/utilities in C/C++/Perl for the IPCAD and DFTM toolkits.
C/C++DFT ToolsIPC Tools

Project Leader

Jul 2006Jun 2008 · 1 yr 11 mos · Kolkata Area, India

  • Developing an Static Timing Analysis tool from scratch using C++.
Static Timing AnalysisC++

Lead Engineer

Jul 2004Jun 2006 · 1 yr 11 mos · Kolkata Area, India

  • Worked on developing various parser from scratch for languages like SPEF, SDF, SAIF, VCD, SDC, LEF, DEF. These parsers were built using Lex, Yacc, C and C++.
  • Also worked on multiple performance improvement projects in the area of RTL Synthesis, Netlist parsing.
C/C++LexYaccParser Development

Education

Jadavpur University

Bachelor of Engineering (B.E.) — Electronics and Communications Engineering

Jan 1995Jan 1999

Stackforce found 100+ more professionals with Hdl Simulation & System Verilog

Explore similar profiles based on matching skills and experience