Tapodyuti Mandal — Software Engineer
Experienced software professional with 20+ years of experience in the EDA tool development. Currently working as Senior Manager at Xilinx and leading the Vivado Simulator (also known as XSIM) India development team. XSIM is a license free software with capabilities similar to other licensed HDL simulators in the EDA world. Key accomplishments include : - Implementing the System Verilog language features Leading the implementation of various complex features such as Class, Virtual Function, Constraint Random, Coverage, Program Block, Clocking Block, Streaming Opertaors, Array Methods etc. - Enablement the UVM features for verification Driving the UVM Enablement initiative. All UVM example designs from Accellera, Dulous and Verification Academy are successfully ported in XSim. - Improve Elaboration and Simulation Performance to match with the standard simulators from other vendors. - LLVM IR generation and optimization for smaller and efficient object code. This is an ongoing project where during elaboration a more properietary and custom IR is generated and that is later transformed into LLVM IR. - Enabling Hardware-in-loop simulation where preverified hardware blocks are placed on the FPGA boards and under development blocks and testbenches are simulated in the standard HDL simulator kernel. - Build the Simulator India development team. Hiring, Coaching and Mentoring a bunch of young and fresh engineers and helping them to grow in a competitive environment. Also had prior experience in working various other EDA tools like Static Timing Analysis, Synthesis, Language Parser, Compiler. Highly proficient in C++, Design Patterns, STL.
Stackforce AI infers this person is a leader in EDA tools with a focus on HDL simulation and performance optimization.
Location: Hyderabad, Telangana, India
Experience: 21 yrs 5 mos
Skills
- Hdl Simulation
- System Verilog
- Team Management
- C/c++
- Dft Tools
- Static Timing Analysis
- Parser Development
Career Highlights
- 20+ years in EDA tool development.
- Led Vivado Simulator development team.
- Expert in System Verilog and UVM implementation.
Work Experience
AMD
Principal Engineer (3 yrs 10 mos)
Xilinx
Senior Manager (4 yrs 11 mos)
Software Engineering Manager (4 yrs 7 mos)
Interra Systems
Manager (4 yrs 3 mos)
Project Leader (1 yr 11 mos)
Lead Engineer (1 yr 11 mos)
Education
Bachelor of Engineering (B.E.) at Jadavpur University