Oct 2021 – Present · 4 yrs 6 mos

• Responsibilities include:
• Design and development of die-2-die(D2D) interconnects for Intel Graphics IPs that are used to facilitate 3D
• stacking technology/ die disaggregated based Architectures.
• Involved in development of BFMs and TB env setup for unit level validation of D2D designs.
• Contributed to the development of IP compiler tool to automate the generation of D2D RTL wrappers and
• rapidly construct the IP configurations from a machine-readable spec. Automation was built and deployed on a
• real-time project and was verified successfully.
• Integration of D2D IPs and handled the delivery of D2D partitions(SD driven) to SOC team.
• Ensured the quality of these partition by running FE static check, debugging functional issues at SOC Val and
• timing closures.
• Coordinated across sites for timely execution and delivery.

May 2019 – Oct 2021 · 2 yrs 5 mos

• Responsibilities include:
• Implementation and Microarchitecture of Network on-chip design.
• Support on automation to improve work efficiency and better turn around for RTL releases.
• Performance analysis- Meeting performance goals of design. Identifying the network topologies that best suits the design. Tuning up NOC buffers and channels width to overcome traffic congestion and to achieve the peak Bandwidth whilst maintaining the area requirements. Performed RTL based performance simulations to get more realistic performance analysis.
• Ensured Quality check on NOC by performing CDC/Lint analysis.
• Performed Logic synthesis and timing analysis on NOC.
• Helped across domain stakeholders (VAL, DFT) in debugging etc.

Jul 2018 – Apr 2019 · 9 mos