Jan 2018 – Jan 2019 · 1 yr

Jan 2017 – Jan 2018 · 1 yr

• Scan insertion flow development using DFT compiler.
• Test pattern generation and verification
• Memory & TCAM test insertion, test pattern generation and verification using Synopsys SMS tool
• Analog IP (Serdes, PLL, etc) test flow development and implementation
• Chip level DFT block(s) design and integration (JTAG TAP controller, Test Control Unit)

Apr 2015 – May 2016 · 1 yr 1 mo

Jan 2015 – Jan 2017 · 2 yrs

• Mbist lead:
• Developed RTL mbist insertion flow and successfully moved the project from Gate level mbist insertion.
• Responsible for RTL memory BIST insertion for server SOC chip.
• Ownership of verification and post-silicon validation of all memory BIST systems across Server IP chips.
• Scan lead:
• Responsible for scan insertion, verification, bug fixes (ECOs), pattern generation for few blocks.
• Co-ordinate cross functional activities across P&R and Timing teams for all DFT related issues.
• Performed coverage analysis (X-reduction) and fed back the results to the design team for next generation chips
• Co-develop efficient test clocking architecture for next server chip.

Jan 2008 – Jan 2009 · 1 yr

• Worked on the development of an ATPG Tool for Path Delay faults. The tool generates Test
• Vectors for Path Delay Faults under the Broad Side Test Application mode.

Jan 2009 – Jan 2015 · 6 yrs · Santa Clara

• DFT lead:
• Performed for test planning, scan insertion, verification, bug fixes (ECOs), pattern generation and silicon bringup on a 28nm Mobile chip.
• Compression planning and insertion with X-tolerance ATPG for coverage improvement.
• Co-ordinated with P&R and timing team on DFT related issues.
• Performed coverage analysis (X-reduction) and fed back the results to the design team for improvement on future products.
• Experience working on Verigy 93K tester platforms.
• New Product Development - Clocks Architecture:
• Redesigned the clock architecture for the next generation GPU & Mobile chips, which improves the test speed significantly.
• This is a major clock architectural change in the history of Nvidia. Deployed the new architecture to three GPU chips and one mobile chip.
• Drive verification and methodology effort with 20 engineers and provide overall management support, training, including plan of record, quality control, documentation and bug management.
• Designing and maintaining On-Chip Clocking (OCC) module, clock divider module and various DFT clock related modules.
• Designed clock controller based shift and capture power reduction logic, worked with synopsys to support these features.
• Methodology:
• Developed verification and pattern generation flow for scan shift power reduction using clock staggering.
• Developed flow for verification and optimized settings generation for low power capture methodology, verified the optimized power settings on ATE.
• Developed verification and Optimization for SERDES (Serializer/Deserializer) self test Scan Architectures.
• Worked with synopsys while evaluating Small Delay Defects and published the findings.
• Clocks Verification:
• Maintaining simulation database and DFT Clock verification using VCS.
• Automated clock monitor identification for DFT verification environment which verifies if the clocks were operating at correct frequency in fast test mode.

Jan 2007 – Jan 2010 · 3 yrs

• Back-end Support for BlackBoard and building course websites.
• Installing and configuring a gene mapping tool to generate Gene-Maps from the research Data.
• The gene tool uses Mysql, Apache server, Perl scripting, Html and CSS.

Jan 2003 – Jan 2008 · 5 yrs

• Full Stack Developer building PHP based applications.
• HTML, CSS, JavaScript, jQuery, PHP
• In depth understanding of OOP
• Web Services
• Agile practices