Saritha Pavuluri

Software Engineer

India22 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC and Functional Verification.
Proven leadership as Principal Engineer at Intel.
Strong background in RTL design and debugging.

Stackforce AI infers this person is a semiconductor design expert with a focus on ASIC and verification technologies.

Contact

Skills

Core Skills

AsicFunctional Verification

Other Skills

SystemVerilogSoCApplication-Specific Integrated Circuits (ASIC)EDADebuggingFPGASemiconductorsRTL codingRTL DesignNCSim

Experience

22 yrs 2 mos

Total Experience

4 yrs 5 mos

Average Tenure

10 yrs 4 mos

Current Experience

Intel tech india pvt ltd

2 roles

Principal Engineer

Promoted

Mar 2022 – Present · 4 yrs 2 mos

SystemVerilogSoCApplication-Specific Integrated Circuits (ASIC)EDADebuggingFPGA+6

Senior Technical Lead

Jan 2016 – Mar 2022 · 6 yrs 2 mos

Amd

2 roles

SMTS

Feb 2015 – Jan 2016 · 11 mos

MTS

Sep 2011 – Jan 2015 · 3 yrs 4 mos

Smartplay

Senior Design Engineer

Sep 2008 – Sep 2011 · 3 yrs

Conexant

Lead Design Engineer

May 2007 – Aug 2008 · 1 yr 3 mos

Intel india technology pvt ltd

Component Design Engineer

Dec 2003 – Apr 2007 · 3 yrs 4 mos

Education

University of North Carolina at Charlotte

Stackforce found 100+ more professionals with Asic & Functional Verification

Explore similar profiles based on matching skills and experience

Ranjith Bidri

Senior Staff Engineer/Manager

at Qualcomm

Bengaluru, India13 yrs 5 mos exp

Sridhar K.

SMTS

at Intel Corporation

Bengaluru, India20 yrs 7 mos exp

VLSIRTL designUSB

Abhishek AH

Senior Member of Technical Staff

at AMD

Bengaluru, India12 yrs 7 mos exp

Engineering

Akash Gupta

Director Silicon Design Engineering

at AMD

Bengaluru, India24 yrs 8 mos exp

VLSISoC

Gurleen Kaur

Member Of Technical Staff

at Mirafra Technologies

India10 yrs 4 mos exp

Hardware Verification

Pratish Behera

DV engineer

at Meta

Bengaluru, India22 yrs 7 mos exp

Chandrashekaraiah V

Senior SoC Design Engineer

at Intel Corporation

Bengaluru, India16 yrs 9 mos exp

Physical DesignTiming Closure

meganathan kumar

Director, Verification & Validation

at Microsoft

Chennai, India14 yrs 3 mos exp