Santhosh G — Software Engineer
Skill set: SV, UVM, Verilog, PERL
Stackforce AI infers this person is a VLSI Verification Engineer with expertise in pre-silicon methodologies.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs 7 mos
Skills
- Universal Verification Methodology (uvm)
- System Verilog
Career Highlights
- Expert in Pre-Si Verification methodologies.
- Proficient in System Verilog and UVM.
- Strong background in VLSI Design.
Work Experience
Intel Corporation
Pre-Si Verification Engineer (7 yrs 4 mos)
Wafer Space
Verification Engineer (1 yr 3 mos)
HCL Technologies
Software Engineer (3 yrs)
Education
Master's degree at Government College of Technology Coimbatore
Bachelor of Engineering (B.E.) at Tamilnadu College of Engineering
