Srujan B V

Software Engineer

Bengaluru, Karnataka, India6 mos experience

Key Highlights

  • Experienced in Static Timing Analysis and VLSI.
  • Strong foundation in ASIC Physical Design.
  • Proficient in advanced design tools and methodologies.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC and Physical Design.

Contact

Skills

Core Skills

Static Timing AnalysisVery-large-scale Integration (vlsi)

Other Skills

LinuxIC Compiler 2Synopsys PrimetimeTiming ClosurePhysical DesignPerlC++Microsoft OfficeMicrosoft PowerPointTeam WorkFloorplanningPlace & RoutePower AnalysisClock Tree SynthesisDesign Rule Checking (DRC)

About

Completed ASIC Physical Design cource in RV-VLSI DESIGN CENTER,BANGLORE. Physical Design Engineer actively looking for an opportunity to work in a professional work driven environment where I can get a platform to utilize as well as improve my knowledge and skills with exposure to advanced technologies while fulfilling organization goals.

Experience

6 mos
Total Experience
6 mos
Average Tenure
--
Current Experience

Mediatek

STA/ SYNTHESIS Engineer

Oct 2019Present · 6 yrs 6 mos · Bangalore

Static Timing AnalysisVery-Large-Scale Integration (VLSI)LinuxIC Compiler 2Synopsys PrimetimeTiming Closure

Rv-vlsi vlsi and embedded systems design center

VLSI Physical Design engineer trainee

Feb 2019Aug 2019 · 6 mos · Bengaluru, India

Education

RV-VLSI DESIGN CENTER

Advance diploma in ASIC design — physical design

Jan 2018Jan 2019

Visvesvaraya Technological University

Bachelor of Engineering- BE — Electronics and Communications Engineering

Jan 2014Jan 2018

Sadvidya Semi Residential PU College

PUC — PCMB

Jan 2012Jan 2014

Stackforce found 100+ more professionals with Static Timing Analysis & Very-large-scale Integration (vlsi)

Explore similar profiles based on matching skills and experience