Venkata KrishnaReddy Kotapati — Software Engineer

Experienced Physical Design Engineer with a demonstrated history of working in VLSI domain. • Overall experience of ~11 years in VLSI Physical Design while delivering more than 8 taped out projects ranging from Intel 22nm, 14nm, 10nm, 7nm, 20A, 18A and TSMC 7nm, 6nm, 3nm technology nodes. • Very good experience in Synthesis, Place & Route, ECO implementation, Low Power, and physical verification on block level P&R closure. • Experience in converging high performance and low power designs with best PPA. • Expertise in Debug and resolving various issues includes synthesis, Floor planning, Placement, Clock Tree Synthesis (CTS), Routing, ECO, Timing closure and Physical verification. • Hands on experience in handling different EDA tools – Innovus, Genus, Tempus, Joules, Design Compiler, ICC/ICC2, Primetime. • Expertise in Leading the projects and guiding the teams in resolving various place and route issues at different stages of design, checklist tracking and flow issues. • Worked for best timing/power/area from Synthesis to Route on low Power and High-Performance Designs and worked on timing correlation issues across the tools and across the stages.

Stackforce AI infers this person is a VLSI Physical Design Engineer with extensive experience in semiconductor technology.

Location: Singapore, Singapore

Experience: 11 yrs 1 mo