Karan patadiya — Software Engineer

I am a dedicated professional with a passion for VLSI (Very Large Scale Integration) technology, constantly driven by the pursuit of innovation in the semiconductor industry. With 2 years of experience in this dynamic domain, I have cultivated a comprehensive understanding of RTL design, verification methodologies. Skills: - 1) Verilog and system Verilog languages. 2) UVM Methodology. 3) Shell scripting and Python. 4) Git-Hub. 5) AMBA protocol , SPI protocol.

Stackforce AI infers this person is a VLSI design engineer with a focus on semiconductor verification.

Location: Ahmedabad, Gujarat, India

Experience: 2 yrs 1 mo