Dhrumil Chag

Product Engineer

Rajkot, Gujarat, India5 yrs 1 mo experience
Highly Stable

Key Highlights

  • 2.5+ years of experience in design verification.
  • Expertise in IP Verification and UVM.
  • Proficient in DDR/LPDDR protocols.
Stackforce AI infers this person is a Semiconductor Verification Engineer with strong expertise in IP verification methodologies.

Contact

LinkedIn

Skills

Other Skills

Application-Specific Integrated Circuits (ASIC)C (Programming Language)Digital ElectronicsLinuxSystemVerilogUniversal Verification Methodology (UVM)VerilogVery-Large-Scale Integration (VLSI)Written Communication

About

Design Verification Engineer at eInfochips with 2.5+ years of experience and good knowledge in IP Verification, System Verilog and UVM. Have a good exposure working with DDR/LPDDR protocols.

Experience

Alphawave semi

VLSI DV Engineer-II

Jun 2024 – Present · 1 yr 9 mos · Pune, Maharashtra, India · Hybrid

  • HBM Controller IP Verification

Einfochips (an arrow company)

Design Verification Engineer

Jan 2021 – May 2024 · 3 yrs 4 mos · Ahmedabad, Gujarat, India

Eitra - einfochips training & research academy ltd

Verification Trainee

Jan 2020 – Dec 2020 · 11 mos · Ahmedabad, Gujarat, India

Education

V.V.P. ENGINEERING COLLEGE, RAJKOT 047

Bachelor of Engineering - BE — Electronics and Communication Engineering

Jan 2016 – Jan 2020

Stackforce found 100+ more professionals with Application-Specific Integrated Circuits (ASIC) & C (Programming Language)

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