Viswanath Bharadwaj

Software Engineer

Hyderabad, Telangana, India13 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 8+ years in SoC verification for AMD
  • Expert in low-power state verification
  • Strong debugging skills in x86 architecture
Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in SoC and debugging.

Contact

Skills

Core Skills

VerificationDebuggingSoc

Other Skills

Boot SequenceVerilogVLSICMatlabSystemVerilogUVMC++LinuxMicrocontrollersEmbedded SystemsSynopsys toolsComputer ArchitectureASIC

About

8+ years of experience in multi-functional teams across SoC involving verification of AMD's x86 based Server SOCs (#Ryzen, #EPYC, #Rome, #Milan, #Milan-X, #Zen, #Zen2, #Zen3, #Zen4, #Zen5). Highly passionate individual with excellent work ethic, laudable communication skills and a great team player. - Good understanding of design and experienced at formulating test-plan strategies identifying all the possible corner cases scenarios involving, multiple-system level end-to-end scenarios. - Experienced in creating coverage plans specific to a design, generating functional and code coverage reports & analyzing them. - Well experienced in planning SoC verification activities, pro-actively assessing the dependencies from IPs, and other functional teams and planning ahead to beat the schedule. - Initially worked extensively on the Design for Debug(DFD) logic functional verification. Highly familiar with the debug bus working, debug data tracing to DRAM and Core debug functionality. - Well versed in enabling debug-functionality of different IPs at SoC to tap the debug data as desired, using JTAG/JTAG-SMN bridge etc. - Conceived various debug recipes for Post-Silicon debugs to isolate the issues seen. - Briefly worked on Post-Silicon debug of the AMDs x86 core, using remote debug tools. - Worked on AMD's infinity fabric low-power verification in the SoC Power Management team. - Worked on CPU low-power states as well as System level low-power states, involving low-power entry of multiple IPs at SoC as well as their power-state operations (involving frequency changes). - Worked extensively in configuring low-power entry mechanisms at SOC involving PCS+PHY's. - Currently working on validation bootcode functionality, Boot Sequence at SoC. - Verified multiple flavors of the bootcode's viz; Multi-Chiplet, Multi-Socket in Server SoC's, on SoC level configurations. - Co-ordinated with multiple involved parties ranging from bootcode-developers to Platform emulation engineers to ensure reliable bootcode, as per the laid-out specifications.

Experience

13 yrs 6 mos
Total Experience
2 yrs 9 mos
Average Tenure
2 yrs 9 mos
Current Experience

Amd

5 roles

Member of Technical Staff

Jul 2023Present · 2 yrs 9 mos

VerificationDebuggingSoCBoot Sequence

Design Engineer 2

Nov 2016Jul 2022 · 5 yrs 8 mos

Senior Design Engineering

Promoted

Nov 2016Jul 2022 · 5 yrs 8 mos

Contractor

Jun 2014Oct 2016 · 2 yrs 4 mos

Contractor

Jul 2013Feb 2014 · 7 mos · Greater Hyderabad Area

  • Worked on x86-debug fails as a part of Core Verification Team.

Intel corporation

Pre Si-Validation Engineer

Jul 2022Jun 2023 · 11 mos

Whizchip design technologies pvt ltd

2 roles

Engineer- VLSI

Jul 2013Oct 2016 · 3 yrs 3 mos

Student Intern

Jul 2012Jun 2013 · 11 mos

  • Worked on the Design and Verification of AMBA APB Subsystem.

Education

Manipal Institute of Technology

Master of Technology (MTech) — Digital Electronics

Jan 2011Jan 2013

Jawaharlal Nehru Technological University, Hyderabad

Bachelor of Technology (BTech) — Electronics and Communication

Jan 2006Jan 2010

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