Shaloo G.

Product Engineer

Uttar Pradesh, India4 yrs experience

Key Highlights

Expert in Static Timing Analysis and Power Estimation.
Hands-on experience with leading EDA tools.
Strong foundation in VLSI Design and Digital Electronics.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Static Timing Analysis and Power Estimation.

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Skills

Core Skills

Static Timing AnalysisParasitic ExtractionPower EstimationLow Power Design

Other Skills

Fusion compilerSynopsys PrimetimeStarRcTCLSiemens- PowerProPTPXDigital ElectronicsRTL CodingVery-Large-Scale Integration (VLSI)Analog Circuit DesignApplication-Specific Integrated Circuits (ASIC)VerilogVHDLMicrosoft WordMicrosoft PowerPoint

Experience

4 yrs

Total Experience

1 yr

Average Tenure

9 mos

Current Experience

Mediatek

Synthesis Engineer

Aug 2025 – Present · 9 mos · On-site

Qualcomm

STA & Extraction CAD Engineer

Jan 2025 – Jul 2025 · 6 mos · On-site

Specialized in developing and supporting static timing and parasitic extraction flows for advanced nodes. Hands-on experience in resolving complex STA issues, flow-related bugs, memory shootout problems, Extraction failures, and tool crashes. Worked closely with Physical design and EDA teams to debug and enhance flow stability and improve runtime and accuracy. Also ensuring proper correlation between Primetime and FC timing reports.

Fusion compilerSynopsys PrimetimeStarRcTCLStatic Timing AnalysisParasitic Extraction

Nxp semiconductors

SoC Low Power Engineer

Jul 2024 – Dec 2024 · 5 mos · Hybrid

Responsible for power estimation for RTL stage, the early power checks to quickly find power issues during RTL development and clock and memory gating to optimize the design for power.
Enabled power analysis at RTL stage from scratch and analysed reports and delivered feedbacks to Verification and RTL teams related to FSDB and ICG cell efficiency.

Siemens- PowerProPTPXPower EstimationLow Power Design