May 2023 – Oct 2023 · 5 mos · Bengaluru, Karnataka, India · Hybrid

Apr 2018 – May 2023 · 5 yrs 1 mo · Bengaluru, Karnataka, India · Hybrid

• SOC Design planning lead for next-generation Server Graphics.
• Translate very early architecture proposals and diagrams into floorplan solutions to enable physical implementation, and meet performance goals while minimizing area / power
• Coordinate placement of all IP’s, high speed IO’s, top level signal planning, and pipelining requirements
• Work closely with SOC Architects to understand product requirements and guide PD team from floorplanning down to tile implementation and fullchip timing closure to meet all required specs
• Lead PD/FEINT activities to optimize PPA, targeting area reduction
• Promote best practices across team and multiple business units
• Lead engagement with packaging teams to plan power delivery and bumps, as well as constraints related to MCM designs with WLFO. Implement floorplan optimizations to improve power-delivery,
• Plan out and enable physical reuse across multiple projects to reduce headcount / resources.
• Work with customer engineering teams on new IPs and propose Physical Design solutions to meet area/timing requirements. Translate high-level specs into actionable PD items.
• Below are key areas as part of SOC design planning.
• 1. SOC floorplan owner for next-generation GPU with 750 mm2 area per tile.
• 2. As part of design planning, I am responsible for area allocation for all subfc/ placement for all
• major IP which includes hbmio/hsphy/mdfic/mdi/fuse/GT-core.
• 3. Global fabric planning for complete SOC
• 4. Directly working with package/PDN to understand HIP placement which has a dependency on
• package routing.
• 5. Feedthrough topology --> Creating feedthrough is the most challenging in SOC db. because of
• complete abutment and multiple star connection and SOC die size.

Dec 2015 – Apr 2018 · 2 yrs 4 mos · Bengaluru Area, India

• Working on FCT setup for the project, handing FC clocks, tiles closer from netlist to gds2 with ICC2 and leading 6 tiles with 2 member team.
• Worked on different blocks of 14nm server chip.
• Responsible for End to End activity of challenging modules of AMD 14nm Server chip.
• Took responsibility for DRC/LVS/Timing closer for most critical tiles on server chip and given back clean database on time.

Jul 2011 – Dec 2014 · 3 yrs 5 mos · Bengaluru Area, India

• Leading Low power design checks for full chip level
• Responsibility added multiple block level designs from Netlist to GDSII
• Understanding architecture of multiple blocks in detail and performing floor-planning of macros
• Responsible for MVRC check for DFP blocks as well as full gnb chip using VSI tool.
• Responsible for writing upf files for Full chip and Block level .

Dec 2014 – Dec 2015 · 1 yr · Bengaluru Area, India

• End-to-End PD Activities

Nov 2010 – Jul 2011 · 8 mos · Bengaluru Area, India

• Texas Instruments (Local Onsite)
• Project Name : Implementation of Micro-controller from Gate level Net list to GDSII.
•  Responsible for subchip and Chip level activities.
•  Full responsibility of one subchip includes Floor plan, Power-plan, Placement, Clock Tree synthesis, Routing, Physical Verification (DRC and LVS clean, EM/IR analysis, Pin placement, Congestion map analysis.
•  Responsible for EM/IR analysis of full chip including manual route at different stages of design.
•  Responsible for manual routing and Resistance calculation of all the manual routes using Star-RCXT and Spice deck analysis.
•  Responsible for Geometric verification and Physical verification at top level.
•  Develop methodology for pin extraction for sub chips from the top level using global router data for reducing the route length and congestion around the sub chips.
•  Responsible for multi floor plan placement of top level macros and subchip level macros at top level to minimize congestion.

Sep 2008 – Nov 2010 · 2 yrs 2 mos

•  2+ years experience in ASIC Physical Design field. Strong Experience in all aspects of IC design including floor planning, power planning, clock tree insertion, place and route, parasitic extraction, Timing Analysis, signal integrity analysis and repair, ECO, Static and Dynamic Voltage drop Analysis and Physical Verification.
•  Strong Experience in Synopsys Astro, IC Compiler and Prime time for Timing Analysis
•  Strong experience in high performance digital design, low power design, high speed clock design and distribution
•  Worked in 0.13u, 90nm technologies having gone through several chip designs from netlist to working silicon
•  Sound understanding of IC Design Concepts, chip level leakage and dynamic power
•  Reduction, chip level Integration, Block Timing closure and Chip level crosstalk analysis
•  Proficient in script writing in Perl and Unix/Linux environment.
•  Strong knowledge in physical design flow, current and future CMOS processes and DFM rules and their implementation
•  Experience in low power circuit techniques (Power Gating, Multi VDD)