T

Tusharkant Mishra

CTO

India20 yrs 8 mos experience
Highly Stable

Key Highlights

  • Senior Technologist with extensive ASIC experience.
  • Expert in Static Timing Analysis and Circuit Design.
  • Proven track record in leading complex engineering projects.
Stackforce AI infers this person is a semiconductor design expert with a focus on ASIC and timing analysis.

Contact

LinkedIn

Skills

Core Skills

Static Timing AnalysisSynthesisSignal IntegrityCircuit DesignPhysical Verification

Other Skills

Place and RouteClock Tree SynthesisStatistical Static Timing AnalysisSTADelay ModellingCustom Circuit DesignSPICE SimulationParasitic ExtractionApplication-Specific Integrated Circuits (ASIC)EDA

Experience

20 yrs 8 mos
Total Experience
3 yrs 2 mos
Average Tenure
1 yr 5 mos
Current Experience

Western digital

Senior Technologist

Dec 2024 – Present · 1 yr 5 mos

Samsung foundry

Associate Director

Jan 2019 – Dec 2024 · 5 yrs 11 mos · Bengaluru, Karnataka, India

Qualcomm

Staff Enginner (Physical Design)

Jun 2015 – Jan 2019 · 3 yrs 7 mos · Bengaluru Area, India

Intel

Component Design Engineer

Jun 2009 – May 2015 · 5 yrs 11 mos · Bengaluru Area, India

Nokia

Sr. Design Engineer ( Consultant )

Oct 2008 – May 2009 · 7 mos

  • Synthesis,STA, Place and Route , Clock Tree Synthesis
SynthesisStatic Timing AnalysisPlace and RouteClock Tree Synthesis

Magma design automation (india) pvt. ltd.

Product Engineer

Jun 2006 – Sep 2008 · 2 yrs 3 mos

  • Statistical Static Timing Analysis , Signal Integrity , STA , Delay Modelling
Statistical Static Timing AnalysisSignal IntegritySTADelay ModellingStatic Timing Analysis

Insilica semiconductors (india) pvt. ltd

Circuit Design Engineer

Jun 2005 – Jun 2006 · 1 yr

  • Custom Circuit Design , SPICE Simulation , Parasitic Extraction , Physical Verification
Custom Circuit DesignSPICE SimulationParasitic ExtractionPhysical VerificationCircuit Design

Education

Indian Institute of Science (IISc)

M.Tech — VLSI Design

Jan 2003 – Jan 2005

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