P

Pradeep Patil

Product Engineer

Pune, Maharashtra, India9 yrs 10 mos experience

Most Likely To Switch

Key Highlights

Expert in Physical Design Engineering with extensive experience.
Proficient in Floor planning and Static Timing Analysis.
Strong automation skills using TCL for design flows.

Stackforce AI infers this person is a Physical Design Engineer specializing in VLSI and ASIC development.

Contact

Skills

Other Skills

Physical DesignSTA and Clock tree synthesisTCLPerlShell ScriptingLinuxProgrammingElectronicsCWiFiApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)Clock Tree SynthesisVerilogSemiconductors

About

Experienced Physical Design Engineer working on block/chip level Floor planning, pin planning, power planning, placement, clock tree synthesis, static timing analysis, routing, IR drop analysis, Parasitic extraction and sign off. Flow automation and stabilizing using tcl.

Experience

9 yrs 10 mos

Total Experience

1 yr 10 mos

Average Tenure

2 yrs 10 mos

Current Experience

Cadence design systems (india) pvt. ltd.

Lead Design Engineer

Jul 2023 – Present · 2 yrs 10 mos

Intel corporation

Sr SOC Design Engineer

May 2022 – Jul 2023 · 1 yr 2 mos · Bengaluru, Karnataka, India

Cadence design systems

Design Engineer II

Mar 2021 – May 2022 · 1 yr 2 mos · Pune, Maharashtra, India

Nvidia

Physical Design Engineer

Oct 2019 – Mar 2021 · 1 yr 5 mos · Bengaluru, Karnataka, India

Graphene semiconductor services pvt ltd.

Physical Design Engineer

Jul 2017 – Mar 2021 · 3 yrs 8 mos · Banglore

Marvell semiconductor

SFQA

Jul 2016 – Jul 2017 · 1 yr

Education

COEP Technological University

Master of Technology (M.Tech.) — VLSI and Embedded system

Jan 2014 – Jan 2016

Govt. College of Engineering Karad

Bachelor's degree — Electronics and Telecommunication

Jan 2010 – Jan 2014

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