Aju Narayanan — Software Engineer
MediaTek leverages my expertise in design verification with UVM and SystemVerilog. With a Master of Engineering in Embedded Systems from BITS Pilani, I bring a strong academic foundation to my work. Motivated by innovation, I focus on ensuring robust verification processes and efficient designs that empower technology teams to deliver high-quality solutions.
Stackforce AI infers this person is a Design Verification Engineer with expertise in image processing and embedded systems.
Location: Thiruvananthapuram, Kerala, India
Experience: 4 yrs 2 mos
Skills
- Universal Verification Methodology (uvm)
- Systemverilog
- Rtl Design
Career Highlights
- Expertise in design verification with UVM and SystemVerilog.
- Strong academic foundation with a Master's in Embedded Systems.
- Proven track record in image quality tuning for camera systems.
Work Experience
MediaTek
Senior Design Verification Engineer (2 yrs 10 mos)
Design Verification Engineer (6 mos)
VVDN Technologies
Software Engineer (1 yr 4 mos)
Education
Master of Engineering - MEng at BITS Pilani, Hyderabad Campus
Bachelor of Technology - BTech at Sree Chitra Thirunal College of Engineering, Pappanamcode, Thiruvananthapuram