Vishnu Priyaa Venkatachalam

Software Engineer

Bengaluru, Karnataka, India3 yrs 3 mos experience

Key Highlights

Expert in IP and system-level verification.
Strong foundation in SystemVerilog and UVM.
Proven track record in debugging and regression execution.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in IP verification and system integration.

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Skills

Core Skills

Ip Verification

Other Skills

SystemVerilogUniversal Verification Methodology (UVM)DisplayPortVerdiJavaScriptPerlSynopsys VerdiLinuxRTL DesignVerilog HDL

About

Senior Verification Engineer with a Master’s in VLSI Design from Vellore Institute of Technology and strong experience in IP and system-level verification. Currently at Qualcomm, working on camera IP top-level verification in a firmware + UVM-based environment, along with verification of key internal sub-blocks supporting system integration. Previously at MediaTek, contributed to DPIN Adapter verification for USB4 v1.0 and v2.0, working across IP-level and co-simulation testbenches. Experienced in constrained-random verification, sequence development, checker and functional coverage implementation, regression execution, and in-depth debugging using Synopsys Verdi. Also involved in verification of DPTX and DP Tunneling. Strong foundation in SystemVerilog, UVM, and Verdi, with a collaborative mindset and a focus on delivering robust, high-quality verification solutions.

Experience

3 yrs 3 mos

Total Experience

1 yr 6 mos

Average Tenure

3 mos

Current Experience

Qualcomm

Senior Engineer

Jan 2026 – Present · 4 mos · Bengaluru, Karnataka, India · On-site

SystemVerilogUniversal Verification Methodology (UVM)IP Verification

Mediatek

2 roles

Senior Verification Engineer

Jul 2023 – Jan 2026 · 2 yrs 6 mos · Bengaluru, Karnataka, India

Worked on verification of DPIN Adapter IP for USB4 v1.0 and v2.0.
Involved in IP-level and co-simulation testbench environments using SystemVerilog and UVM.
Actively contributed to constrained-random verification through sequence development and enhancements, along with implementation of checkers and functional coverage.
Executed and stabilized regressions, and performed in-depth debugging of failures using Verdi waveform analysis, collaborating closely with design teams to ensure USB4 protocol compliance, backward compatibility, and overall design robustness.

DisplayPortIP VerificationSystemVerilogUniversal Verification Methodology (UVM)Verdi